SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 147

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
18.1.3.2 Hardware retry mechanism
18.2.1 Problem description
18.2.2 Implication
18.2.3 Workaround
18.3.1 Problem description
18.2 Errata added on 2009-04-20
18.3 Errata added on 2009-04-20
Set program register RL = 0000b, NakCnt = 0000b and Cerr = 10b. In this case, interrupt
will not be generated for NAKs and hardware will retry indefinitely, until the device
responds with a data or an ACK.
When at least two USB devices are simultaneously running, it is observed that sometimes
the INT corresponding to one of the USB devices stops occurring. This may be observed
sometimes with USB-to-serial or USB-to-network devices.
The problem is not noticed when only USB mass storage devices are running.
This issue is because of the clearing of the respective Done Map bit on reading the ATL
PTD Done Map register when an INT is generated by another PTD completion, but is not
found set on that read access. In this situation, the respective Done Map bit will remain
reset and no further INT will be asserted, so the data transfer corresponding to that USB
device will stop.
An SOF INT can be used instead of an ATL INT with polling on Done bits. A time-out can
be implemented and if a certain Done bit is never set, verification of the PTD completion
can be done by reading PTD contents (valid bit).
The DMA Transfer Counter register of the Peripheral Controller is decremented by
4 bytes or 2 bytes even when it sees a short packet, which is not a multiple of 4 bytes or
2 bytes. Because of the extra count decremented and written to the buffer, the buffer does
not reflect the correct amount of data. The Peripheral Controller recognizes how many
data bytes are received in either of these ways:
•
•
Option 1: The host informs the peripheral about the number of bytes that will be
transferred before sending the data bytes. The mass storage class supports this type
of transfer. This option is properly handled even if the transfer counter is programmed
in odd numbers.
Option 2: The peripheral does not know beforehand how many bytes will be received.
On receiving a short packet or a zero-length packet, the peripheral checks data bytes
number from the USB chip DMA counter after DMA completion. An example is a
printer application. The printing class supports this type of transfer; see
Rev. 01 — 18 November 2009
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
Figure
147 of 166
30.