SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 85

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
9.3.1 B-device initiating SRP
9.3.2 A-device responding to SRP
9.3 Session Request Protocol (SRP)
peripheral, and the A-device assumes the role of a host. The A-device detects that the
B-device can support HNP by getting the OTG descriptor from the B-device. The A-device
will then enable the HNP hand-off by using SetFeature (b_hnp_enable) and then go into
the suspend state. The B-device signals claiming the host role by de-asserting its pull-up
resistor. The A-device acknowledges by going into the peripheral state. The B-device then
assumes the role of a host and communicates with the A-device as long as it wishes.
When the B-device finishes communicating with the A-device, both devices finally go into
the idle state. See
As a dual-role device, the SAF1761 can initiate and respond to SRP. The B-device
initiates SRP by data line pulsing, followed by V
either data line pulsing or V
The SAF1761 can initiate SRP by performing the following steps:
The B-device must complete both data line pulsing and V
The A-device must be able to respond to one of the two SRP events: data line pulsing or
V
means that the peripheral-only device must initiate data line pulsing through DP. A
dual-role device will always initiate data line pulsing through DP.
To enable the SRP detection through the V
OTG Interrupt Enable Fall and OTG Interrupt Enable Rise registers.
To enable the SRP detection through the DP pulsing, set DP_SRP (bit 2) in the OTG
Interrupt Enable Rise register.
1. Detect initial conditions [read B_SESS_END and B_SE0_SRP (bits 7 and 8) of the
2. Start data line pulsing [set DP_PULLUP (bit 0) of the OTG Control (set) register to
3. Wait for 5 ms to 10 ms.
4. Stop data line pulsing [set DP_PULLUP (bit 0) of the OTG Control (clear) register to
5. Start V
6. Wait for 10 ms to 20 ms.
7. Stop V
8. Discharge V
BUS
OTG Status register].
logic 1].
logic 0].
logic 1].
logic 0].
Control (set) register], optional.
pulsing. When data line pulsing is used, the SAF1761 can detect DP pulsing. This
BUS
BUS
pulsing [set VBUS_CHRG (bit 6) of the OTG Control (clear) register to
pulsing [set VBUS_CHRG (bit 6) of the OTG Control (set) register to
BUS
Figure 14
for about 30 ms [by using VBUS_DISCHRG (bit 5) of the OTG
Rev. 01 — 18 November 2009
BUS
and
pulsing.
Figure
15.
BUS
pulsing, set A_B_SESS_VLD (bit 1) in the
BUS
pulsing. The A-device can detect
BUS
Hi-Speed USB OTG controller
pulsing within 100 ms.
SAF1761
© NXP B.V. 2009. All rights reserved.
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