SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 141

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
Fig 27. DMA read or write
(write) DATA [31 :0 ]
(read) DATA [31 :0 ]
RD_N/WR_N
DREQ is continuously asserted until the last transfer is done or the FIFO is full.
Data strobes: RD_N (read) and WR_N (write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
DREQ
DACK
15.2.2.1 DMA read or write
15.2.2 DMA timing
(2)
(1)
Table 178. DMA read or write
T
Symbol Parameter
V
T
t
t
t
t
t
t
t
t
t
t
t
V
T
t
t
t
su19
d19
h19
w19
w29
d29
h29
h39
su29
su39
a19
su19
d19
amb
su39
cy19
cy19
CC(I/O)
CC(I/O)
t
su19
= 40 C to +85 C; unless otherwise specified.
= 1.65 V to 1.95 V
= 3.3 V to 3.6 V
read or write cycle time
DREQ set-up time before first DACK on
DREQ on delay after last strobe off
DREQ hold time after last strobe on
RD_N/WR_N pulse width
RD_N/WR_N recovery time
read data valid delay after strobe on
read data hold time after strobe off
write data hold time after strobe off
write data set-up time before strobe off
DACK set-up time before RD_N/WR_N assertion
DACK de-assertion after RD_N/WR_N
de-assertion
read or write cycle time
DREQ set-up time before first DACK on
DREQ on delay after last strobe off
t
d29
t
w19
t
su29
Rev. 01 — 18 November 2009
t
h29
t
w29
t
h39
T
cy19
Min
75
10
33.33
0
40
36
-
-
1
10
0
3
75
10
33.33
t
h19
Hi-Speed USB OTG controller
t
a19
Max
-
-
-
53
600
-
30
5
-
-
-
-
-
-
-
SAF1761
© NXP B.V. 2009. All rights reserved.
t
d19
004aaa528
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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