SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 136

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
15.1.2.2 Single cycle: DMA write
Table 172. DMA read (single cycle)
T
Table 173. DMA write (single cycle)
T
Symbol
t
t
t
Symbol
V
t
t
t
t
t
t
t
t
V
t
t
t
t
t
t
t
t
a34
a44
h14
a15
a25
h15
h25
su15
a35
cy15
w15
a15
a25
h15
h25
su15
a35
cy15
w15
amb
amb
Fig 22. DMA write (single cycle)
CC(I/O)
CC(I/O)
= 40 C to +85 C; unless otherwise specified.
= 40 C to +85 C; unless otherwise specified.
= 1.65 V to 1.95 V
= 3.3 V to 3.6 V
DREQ
WR_N
DREQ and DACK are active HIGH.
DACK
DATA
Parameter
DREQ de-assertion time after RD_N assertion
DACK de-assertion to next DREQ assertion time -
data hold time after RD_N de-asserts
Parameter
DACK assertion time after DREQ assertion
WR_N assertion time after DACK assertion
data hold time after WR_N de-assertion
DACK hold time after WR_N de-assertion
data set-up time before WR_N de-assertion
DREQ de-assertion time after WR_N assertion
last DACK strobe de-assertion to next DREQ
assertion time
WR_N pulse width
DACK assertion time after DREQ assertion
WR_N assertion time after DACK assertion
data hold time after WR_N de-assertion
DACK hold time after WR_N de-assertion
data set-up time before WR_N de-assertion
DREQ de-assertion time after WR_N assertion
last DACK strobe de-assertion to next DREQ
assertion time
WR_N pulse width
Rev. 01 — 18 November 2009
t
a25
t
a15
t
a35
t
w15
…continued
t
su15
data
t
h25
t
cy15
t
h15
Min
-
-
Hi-Speed USB OTG controller
Min
0
1
3
0
5.5
-
-
22
0
1
2
0
5.5
-
-
22
data 1
Max
18
56
5
Max
-
-
-
-
-
28
82
-
-
-
-
-
-
16
82
-
SAF1761
© NXP B.V. 2009. All rights reserved.
004aaa525
Unit
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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