CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet
CY8CKIT-050
Specifications of CY8CKIT-050
Related parts for CY8CKIT-050
CY8CKIT-050 Summary of contents
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... C • Many others available in catalog Notes 1. GPIOs with opamp outputs are not recommended for use with CapSense. 2. This feature on select devices only. See Ordering Information on page 106 Cypress Semiconductor Corporation Document Number: 001-66235 Rev. *A PRELIMINARY ® PSoC 5: CY8C55 Family Datasheet Programmable System-on-Chip (PSoC ® ...
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Contents 1. Architectural Overview .................................................... 3 2. Pinouts .............................................................................. 5 3. Pin Descriptions ............................................................... 9 4. CPU .................................................................................. 10 4.1 ARM Cortex-M3 CPU .............................................. 10 4.2 Cache Controller ..................................................... 11 4.3 DMA and PHUB ...................................................... 12 5. Memory ............................................................................ 16 ...
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Architectural Overview Introducing the CY8C55 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C55 family provides configurable blocks of analog, digital, and interconnect circuitry ...
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Figure 1-1 illustrates the major components of the CY8C55 family. They are: ■ ARM Cortex-M3 CPU subsystem ■ Nonvolatile subsystem ■ Programming, debug, and test subsystem ■ Inputs and outputs ■ Clocking ■ Power ■ Digital subsystem ■ Analog subsystem ...
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PSoC’s nonvolatile subsystem consists of flash and byte-writeable EEPROM. It provides up to 256 KB of on-chip flash. The CPU can reprogram individual blocks of flash, enabling boot loaders. A powerful and flexible protection model secures the user's sensitive information, ...
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P2[6] 1 (GPIO) P2[7] 2 (SIO) P12[4] 3 (SIO) P12[5] 4 Vssb 5 Ind 6 Vboost 7 Vbat 8 Vssd 9 10 XRES (SWDIO, GPIO) P1[0] 11 (SWDCK, GPIO) P1[1] 12 (GPIO) P1[2] 13 (SWV, GPIO) P1[3] 14 (GPIO) ...
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P2[5] 1 (GPIO) P2[6] 2 (GPIO) P2[7] 3 Lines show Vddio (I2C0: SCL, SIO) P12[ I/O supply (I2C0: SDA, SIO) P12[5] 5 association (GPIO) P6[4] 6 (GPIO) P6[5] 7 (GPIO) P6[6] 8 (GPIO) P6[7] 9 Vssb 10 ...
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Figure 2-3. Example Schematic for 100-pin TQFP Part with Power Connections Vddd C6 0.1 uF Vssd 1 P2[5] 2 P2[6] 3 P2[7] 4 P12[4], SIO 5 P12[5], SIO 6 P6[4] 7 P6[5] 8 P6[6] 9 P6[7] 10 Vssb 11 Ind ...
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Figure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance Vssd Plane 3. Pin Descriptions IDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin for high-current DACs (IDAC). OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out. High [6] current output of uncommitted opamp. ...
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CPU 4.1 ARM Cortex-M3 CPU The CY8C55 family of devices has an ARM Cortex-M3 CPU core. The Cortex- low-power 32-bit three-stage pipelined Harvard-architecture CPU that delivers 1.25 DMIPS/MHz intended for deeply embedded applications that require ...
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The Cortex-M3 does not support ARM instructions. ■ Bit-band support. Atomic bit-level write and read operations. ■ Unaligned data storage and access. Contiguous storage of data of different byte lengths. ■ Operation at two privilege levels (privileged and user) and ...
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DMA and PHUB The PHUB and the DMA controller are responsible for data transfer between the CPU and peripherals, and also data transfers between peripherals. The PHUB and DMA also control device configuration during boot. The PHUB consists of: ...
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ADDRESS Phase CLK ADDR 16/32 A WRITE DATA READY Basic DMA Read Transfer without wait states 4.3.4.2 Auto Repeat DMA Auto repeat DMA is typically used when a static pattern is repetitively read from system memory and written to a ...
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Interrupt Controller The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table 4-6. Cortex-M3 Exceptions and Interrupts Exception Exception Type Number 1 Reset -3 (highest) 2 NMI -2 3 Hard fault -1 4 ...
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Table 4-7. Interrupt Vector Table Interrupt # Cortex-M3 Exception # ...
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Memory 5.1 Static RAM CY8C55 static RAM (SRAM) is used for temporary data storage. Code can be executed at full speed from the portion of SRAM that is located in the code space. This process is slower from SRAM ...
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Memory Map The Cortex-M3 has a fixed address map, which allows peripherals to be accessed by simple memory access instructions. 5.5.1 Address Map The 4-GB address space is divided into the ranges shown in Table 5-2: Table 5-2. Address ...
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System Integration 6.1 Clocking System The clocking system generates, divides, and distributes clocks throughout the PSoC system. For the majority of systems, no external crystal is required. The IMO and PLL together can generate MHz ...
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Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin IMO 3 MHz ±4% over voltage and temperature MHzECO 4 MHz Crystal dependent DSI 0 MHz Input dependent PLL 24 MHz Input dependent Doubler 48 MHz Input dependent ILO 1 kHz ...
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The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL outputs clock frequencies in the range MHz. Its input and feedback dividers supply 4032 discrete ratios to ...
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This is only possible if there are multiple precision clock sources. 6.1.3 Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system ...
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Vddio2 0.1 µF I/O Supply Digital Domain Vssb I/O Supply 0.1 µF Vddio1 Note The two V pins must be connected together with as short a trace as possible. A trace under the device is recommended, as CCD shown in ...
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Table 6-2. Power Modes Power Modes Description Active Primary mode of operation, all peripherals available (program- mable) Alternate Similar to Active mode, and is Active typically configured to have fewer peripherals active to reduce power. One possible configuration is to ...
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Alternate Active Mode Alternate Active mode is very similar to Active mode. In alternate active mode, fewer subsystems are enabled, to reduce power consumption. One possible configuration is to turn off the CPU and flash, and run peripherals at ...
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Reset CY8C55 has multiple internal and external reset sources available. The reset sources are: ■ Power source monitoring - The analog and digital power voltages and V DDA DDD CCA CCD several different ...
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I/O System and Routing PSoC I/Os are extremely flexible. Every GPIO has analog and digital I/O capability. All I/Os have a large number of drive modes, which are set at POR. PSoC also provides up to four individual I/O ...
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Digital Input Path PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Analog Capsense Global Control CAPS[x]CFG1 PRT[x]AG Analog Global Enable ...
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Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Digital Input Path ...
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Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts ...
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Resistive Pull-up or Resistive Pull-down Resistive pull-up or pull-down, respectively, provides a series resistance in one of the data states and strong drive in the other. Pins can be used for digital input and output in these modes. Interfacing ...
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Adjustable Output Level This section applies only to SIO pins. SIO port pins support the ability to provide a regulated high output level for interface to external signals that are lower in voltage than the SIO’s respective V . ...
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Special Pin Functionality Some pins on the device include additional special functionality in addition to their GPIO or SIO functionality. The specific special function pins are listed in “Pinouts” on page 5. The special features are: ■ Digital ❐ ...
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Example Analog Components The following is a sample of the analog components available in PSoC Creator for the CY8C55 family. The exact amount of hardware resources (SC/CT blocks, routing, RAM, flash) used by a component varies with the features ...
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Document Number: 001-66235 Rev. *A PRELIMINARY ® PSoC 5: CY8C55 Family Datasheet Figure 7-2. PSoC Creator Framework Page 34 of 114 [+] Feedback ...
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Component Catalog Figure 7-3. Component Catalog The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device populated with an impressive selection of content; from simple primitives such as ...
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Universal Digital Block The Universal Digital Block (UDB) represents an evolutionary step to the next generation of PSoC embedded digital peripheral functionality. The architecture in first generation PSoC digital blocks provides coarse programmability in which a few fixed functions ...
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Input Muxes Input from Programmable Routing 6 PI Parallel Input/Output (To/From Programmable Routing) PO 7.2.2.1 Working Registers The datapath contains six primary working registers, which are accessed by CPU firmware or DMA during normal operation. Table 7-1. Working Datapath Registers ...
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Conditionals Each datapath has two compares, with bit masking options. Compare operands include the two accumulators and the two data registers in a variety of configurations. Other conditions include zero detect, all ones detect, and overflow. These conditions are ...
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UDB Array Description Figure 7-11 shows an example UDB array. In addition to the array core, there are a DSI routing interfaces at the top and bottom of the array. Other interfaces that are not explicitly ...
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Figure 7-13. Digital System Interconnect Timer Interrupt DMA CAN I2C Counters Controller Controller Digital System Routing I/F UDB ARRAY Digital System Routing I/F Global IO Port SC/CT Del-Sig Clocks Pins Blocks Interrupt and DMA routing is very flexible in the ...
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CAN The CAN peripheral is a fully functional Controller Area Network (CAN) supporting communication baud rates Mbps. The CAN controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the ...
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Tx Buffer Status TxReq Pending TxInterrupt Request (if enabled) RxMessage0 Rx Buffer Status RxMessage RxMessage1 Available RxMessage14 RxInterrupt RxMessage15 Request (if enabled) 7.6 USB PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 transceiver supporting all four USB transfer types: ...
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The Timer/Counter/PWM peripheral can select from multiple clock sources, with input and output signals connected through the DSI routing. DSI routing allows input and output connections to any device pin and any internal digital signal accessible through the DSI. Each ...
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Digital Filter Block Some devices in the CY8C55 family of devices have a dedicated HW accelerator block used for digital filtering. The DFB has a dedicated multiplier and accumulator that calculates a 24-bit by 24-bit multiply accumulate in one ...
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GPIO O Port The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and also connections ...
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Analog Routing The CY8C38 family of devices has a flexible analog routing architecture that provides the capability to connect GPIOs and different analog blocks, and also route signals between different analog blocks. One of the strong points of this ...
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ExVrefL ExVrefL1 swinp GPIO P0[4] swinn GPIO P0[5] GPIO * i0 P0[6] GPIO i2 * P0[7] cmp0_vref (1.024V) GPIO cmp_muxvn[1:0] P4[2] vref_cmp1 bg_vda_res_en GPIO Vdda Vdda/2 P4[3] refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) GPIO P4[4] GPIO P4[5] GPIO P4[6] GPIO ...
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Delta-sigma ADC The CY8C38 device contains one delta-sigma ADC. This ADC offers differential input, high resolution and excellent linearity, making it a good ADC choice for both audio signal processing and measurement applications. The converter's nominal operation is 16 ...
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Continuous Continuous sample mode is used to take multiple successive samples of a single input signal. Multiplexing multiple inputs should not be done with this mode. There is a latency of three conversion times before the first conversion result ...
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Input and Output Interface The positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus and precision reference through multiplexers. The output from each comparator could be routed ...
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Opamps The CY8C55 family of devices contain four general purpose opamps. Figure 8-8. Opamp GPIO Analog Global Bus Opamp Analog Global Bus VREF Analog Internal Bus = GPIO The opamp is uncommitted and can be configured as a gain ...
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PGA The PGA amplifies an external or internal signal. The PGA can be configured to operate in inverting mode or noninverting mode. The PGA function may be configured for both positive and negative gains as high as 50 and ...
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Figure 8-12. LCD System LCD Global DAC Clock UDB LCD Driver Block Display DMA RAM PHUB 8.7.1 LCD Segment Pin Driver Each GPIO pin contains an LCD driver circuit. The LCD driver buffers the appropriate output of the LCD DAC ...
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Reference Source 8.10.1 Current DAC The current DAC (IDAC) can be configured for the ranges µ 256 µA, and 0 to 2.04 mA. The IDAC can be configured to source or sink current. 8.10.2 Voltage ...
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Programming, Debug Interfaces, Resources The Cortex-M3 has internal debugging components, tightly integrated with the CPU, providing the following features: ■ SWD access ■ Flash Patch and Breakpoint (FPB) block for implementing breakpoints and code patches ■ Data Watchpoint and ...
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Figure 9-1. SWD Interface Connections between PSoC 5 and Programmer Host Programmer 1 The voltage levels of the Host Programmer and the PSoC 5 voltage domains involved in programming should be the same. XRES pin is powered by V programming ...
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Debug Features The CY8C55 supports the following debug features: ■ Halt and single-step the CPU ■ View and change CPU and peripheral registers, and RAM addresses ■ Six program address breakpoints and two literal access breakpoints ■ Data watchpoint ...
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Development Support The CY8C55 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more. 10.1 Documentation A suite of documentation, to ensure that you ...
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Electrical Specifications Specifications are valid for -40 °C ≤ T ≤ 85 °C and T A where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see ...
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Device Level Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description V Analog supply voltage and input to analog core DDA ...
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Table 11-3. AC Specifications Parameter Description F CPU frequency CPU F Bus frequency BUSCLK Svdd V ramp rate DD T Time from IO_INIT DDD DDA CCD ≥ IPOR to I/O ports set to their reset states ...
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Power Regulators Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description V Input voltage DDD V Output voltage CCD ...
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Analog Core Regulator Table 11-5. Analog Core Regulator DC Specifications Parameter Description V Input voltage DDA V Output voltage CCA Regulator output capacitor Figure 11-3. Analog Regulator PSRR vs Frequency and V Document Number: 001-66235 Rev. *A PRELIMINARY ® ...
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Inductive Boost Regulator. Table 11-6. Inductive Boost Regulator DC Specifications Unless otherwise specified, operating conditions are µF || 0.1 µF BOOST Parameter Description V Input voltage BAT Includes startup [18, 19] I Load current OUT ...
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Table 11-8. Recommended External Components for Boost Circuit Parameter Description L Boost inductor BOOST [22] C Filter capacitor BOOST I External Schottky diode F average forward current V R 11.4 Inputs and Outputs Specifications are valid for –40 °C ≤ ...
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Figure 11-4. GPIO Output High Voltage and Current Table 11-10. GPIO AC Specifications Parameter Description TriseF Rise time in Fast Strong Mode TfallF Fall time in Fast Strong Mode TriseS Rise time in Slow Strong Mode TfallS Fall time in ...
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SIO Table 11-11. SIO DC Specifications Parameter Description Vinmax Maximum input voltage Vinref Input voltage reference (differential input mode) Output voltage reference (regulated output mode) Voutref Input voltage high threshold V GPIO mode IH [24] Differential input mode Input ...
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Figure 11-8. SIO Output High Voltage and Current, Unregulated Mode Figure 11-10. SIO Output High Voltage and Current, Regulat- ed Mode Table 11-12. SIO AC Specifications Parameter Description TriseF Rise time in fast strong mode [26] (90/10%) TfallF Fall time ...
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Table 11-12. SIO AC Specifications (continued) Parameter Description SIO output operating frequency Unregulated output (GPIO) mode, fast strong drive mode 3.3 V < V < 5.5 V, Unregu- DDIO lated output (GPIO) mode, slow strong drive mode Fsioout 2.7 V ...
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USBIO For operation in GPIO mode, the standard range for V Table 11-13. USBIO DC Specifications Parameter Description Rusbi USB D+ pull-up resistance Rusba USB D+ pull-up resistance Vohusb Static output high Volusb Static output low Vihgpio Input voltage ...
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Table 11-14. USBIO AC Specifications Parameter Description Tdrate Full-speed data rate average bit rate Tjr1 Receiver data jitter tolerance to next transition Tjr2 Receiver data jitter tolerance to pair transition Tdj1 Driver differential jitter to next transition Tdj2 Driver differential ...
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XRES Table 11-16. XRES DC Specifications Parameter Description V Input voltage high threshold IH V Input voltage low threshold IL Rpullup Pull-up resistor [27] C Input capacitance IN V Input voltage hysteresis H [27] (Schmitt-Trigger) Idiode Current through protection ...
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Analog Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.5.1 Opamp Table 11-18. Opamp DC Specifications Parameter Description V Input offset voltage IOFF Vos Input offset voltage TCVos Input offset ...
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Figure 11-18. Opamp Voffset vs Vcommon and Vdda, 25 °C Figure 11-20. Opamp Operating Current vs Vdda and Power Mode O Table 11-19. Opamp AC Specifications Parameter Description GBW Gain-bandwidth product SR Slew rate, 20% - 80% e Input noise ...
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Figure 11-21. Opamp Noise vs Frequency, Power Mode = High, Vdda = 5V Figure 11-23. Opamp Step Response, Falling Document Number: 001-66235 Rev. *A PRELIMINARY ® PSoC 5: CY8C55 Family Datasheet Figure 11-22. Opamp Step Response, Rising Page 75 of ...
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Delta-Sigma ADC Unless otherwise specified, operating conditions are: ■ Operation in continuous sample mode ■ fclk = 3.072 MHz for resolution = bits; fclk = 6.144 MHz for resolution = bits ■ Reference ...
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Table 11-20. 20-bit Delta-sigma ADC DC Specifications (continued) Parameter Description Rin_ADC16 ADC input resistance Rin_ADC12 ADC input resistance ADC external reference input voltage, see Vextref also internal reference in Voltage Reference on page 80 Current Consumption I Current consumption, 20 ...
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Table 11-22. Delta-sigma ADC Sample Rates, Range = ±1.024 V Continuous Resolution, Bits Min 8 8000 9 6400 10 5566 11 4741 12 4000 13 3283 14 2783 15 2371 16 2000 17 500 18 125 ...
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Figure 11-26. Delta-sigma ADC Noise Histogram, 1000 sam- ples, 16-bit, 48 ksps, Ext Ref REF Table 11-23. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Single Ended Sample rate, ...
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Table 11-26. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 20-bit, External Reference, Differential Sample rate, sps ±VREF 8 0.70 11.3 0.69 22.5 0.73 45 0.76 61 0.75 170 0.75 187 0.73 Figure 11-28. Delta-sigma ADC ...
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SAR ADC Table 11-28. SAR ADC DC Specifications Parameter Description Resolution Number of channels – single-ended Number of channels – differential [33] Monotonicity Ge Gain error V Input offset voltage OS I Current consumption DD Input voltage range – ...
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Comparator Table 11-31. Comparator DC Specifications Parameter Description Input offset voltage in fast mode V OS Input offset voltage in slow mode Input offset voltage in fast mode V OS Input offset voltage in slow mode V Input offset ...
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Current Digital-to-analog Converter (IDAC) See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-33. IDAC DC Specifications Parameter Description Resolution I Output ...
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Table 11-33. IDAC DC Specifications (continued) Parameter Description I Operating current, code = 0 DD Figure 11-30. IDAC INL vs Input Code, Range = 255 µA, Source Mode Document Number: 001-66235 Rev. *A PRELIMINARY ® PSoC 5: CY8C55 Family Datasheet ...
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Figure 11-32. IDAC DNL vs Input Code, Range = 255 µA, Source Mode Figure 11-34. IDAC INL vs Temperature, Range = 255 µA, Fast Mode Document Number: 001-66235 Rev. *A PRELIMINARY ® PSoC 5: CY8C55 Family Datasheet Figure 11-33. IDAC ...
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Figure 11-36. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode Figure 11-38. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode Document Number: 001-66235 Rev. *A PRELIMINARY ® PSoC 5: CY8C55 ...
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Table 11-34. IDAC AC Specifications Parameter Description F Update rate DAC T Settling time to 0.5 LSB SETTLE Figure 11-40. IDAC Step Response, Codes 0x40 - 0xC0, 255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V Figure 11-42. ...
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Voltage Digital to Analog Converter (VDAC) See the VDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-35. VDAC DC Specifications Parameter Description Resolution ...
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Figure 11-45. VDAC INL vs Temperature Mode Figure 11-47. VDAC Full Scale Error vs Temperature Mode Figure 11-49. VDAC Operating Current vs Temperature, 1V Mode, Slow Mode Document Number: 001-66235 Rev. *A PRELIMINARY ® PSoC 5: ...
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Table 11-36. VDAC AC Specifications Parameter Description F Update rate DAC TsettleP Settling time to 0.1%, step 25% to 75% TsettleN Settling time to 0.1%, step 75% to 25% Figure 11-51. VDAC Step Response, Codes 0x40 - 0xC0 ...
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Mixer The mixer is created using a SC/CT analog block; see the Mixer component data sheet in PSoC Creator for full electrical specifications and APIs. Table 11-37. Mixer DC Specifications Parameter Description V Input offset voltage OS Quiescent current ...
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Programmable Gain Amplifier The PGA is created using a SC/CT analog block; see the PGA component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, operating conditions are: ■ Operating temperature = 25 °C ...
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Table 11-42. PGA AC Specifications Parameter Description BW1 –3 dB bandwidth SR1 Slew rate e Input noise density n Figure 11-55. Bandwidth vs. Temperature, at Different Gain Settings, Power Mode = High 11.5.12 Temperature Sensor Table 11-43. Temperature Sensor Specifications ...
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Table 11-45. LCD Direct Drive AC Specifications Parameter Description f LCD frame rate LCD 11.6 Digital Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.6.1 Timer The following specifications apply to ...
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Table 11-49. Counter AC Specifications (continued) Parameter Description Pulse width Pulse width (external) Enable pulse width Enable pulse width (external) Reset pulse width Reset pulse width (external) 11.6.3 Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in ...
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Controller Area Network Table 11-54. CAN DC Specifications Parameter Description I Block current consumption DD Table 11-54. CAN AC Specifications Parameter Description Bit rate 11.6.5 Digital Filter Block Table 11-55. DFB DC Specifications Parameter Description DFB operating current Table ...
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USB Table 11-57. USB DC Specifications Parameter Description V Device supply for USB operation USB_5 V USB_3.3 V USB_3 I Device supply current in device active USB_Configured mode, bus clock and IMO = 24 MHz I Device supply current ...
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Memory Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.7.1 Flash Table 11-59. Flash DC Specifications Parameter Description Erase and program voltage Table 11-60. Flash AC Specifications Parameter Description T Row ...
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EEPROM Table 11-61. EEPROM DC Specifications Parameter Description Erase and program voltage Table 11-62. EEPROM AC Specifications Parameter Description T Single row erase/write cycle time WRITE EEPROM data retention time, retention period measured from last erase cycle 11.7.3 SRAM ...
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PSoC System Resources Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.8.1 Voltage Monitors Table 11-65. Voltage Monitors DC Specifications Parameter Description LVI Trip voltage LVI_A/D_SEL[3:0] = 0011b LVI_A/D_SEL[3:0] = 0100b ...
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SWD Interface Table 11-68. SWD Interface AC Specifications Parameter Description f_SWDCK SWDCLK frequency T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max T_SWDI_hold SWDIO input hold after SWDCK high T_SWDO_valid SWDCK high to SWDIO output T_SWDO_hold SWDIO ...
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Clocking Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. Unless otherwise specified, all charts and graphs show typical values. 11.9.1 32 kHz External Crystal Table 11-70. 32 kHz External Crystal DC ...
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Table 11-76. IMO AC Specifications Parameter Description IMO frequency stability (with factory trim) 62.6 MHz 48 MHz F 24 MHz IMO 12 MHz 6 MHz 3 MHz [44] Startup time [45] Jitter (peak to peak) Jp MHz ...
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Internal Low Speed Oscillator Table 11-77. ILO DC Specifications Parameter Description Operating current I CC Leakage current Table 11-78. ILO AC Specifications Parameter Description Startup time, all frequencies ILO frequencies (trimmed) 100 kHz 1 kHz F ILO ILO frequencies ...
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External Crystal Oscillator Table 11-79. ECO AC Specifications Parameter Description F Crystal frequency range 11.9.5 External Clock Reference Table 11-80. External Clock Reference AC Specifications Parameter Description External frequency range Input duty cycle range Input edge rate 11.9.6 Phase-Locked ...
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Ordering Information In addition to the features listed in Table precision on-chip voltage reference, precision oscillators, flash, DMA, a fixed function I In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. ...
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Examples 5: PSoC 5 5: CY8C55 Family Family Group within Architecture 8: 80 MHz 8: 256 KB AX: TQFP I: Industrial All devices in the PSoC 5 CY8C55 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free ...
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Packaging Table 13-1. Package Characteristics Parameter Description T Operating ambient temperature A T Operating junction temperature J Package θJA (68-pin QFN) Tja Package θJA (100-pin TQFP) Tja Package θJC (68-pin QFN) Tjc Package θJC (100-pin TQFP) Tjc Table 13-2. ...
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Figure 13-2. 100-pin TQFP ( 1.4 mm) Package Outline Document Number: 001-66235 Rev. *A PRELIMINARY ® PSoC 5: CY8C55 Family Datasheet 51-85048 *E Page 109 of 114 [+] Feedback ...
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Acronyms Table 14-1. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus archi- tecture) high-performance bus, an ARM data transfer bus ALU arithmetic logic unit AMUXBUS ...
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Table 14-1. Acronyms Used in this Document (continued) Acronym Description PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration datasheet POR power-on reset PRS pseudo random sequence PS port read data ...
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Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz kΩ kilohms ksps kilosamples ...
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Revision History ® Description Title: PSoC 5: CY8C55 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-66235 Submission Rev. ECN No. Date ** 3198501 03/17/2011 *A 3279676 06/10/2011 Document Number: 001-66235 Rev. *A PRELIMINARY ® PSoC 5: CY8C55 Family Datasheet ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...