CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 20

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 67 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
almost any desired system clock frequency. The accuracy of the
PLL output depends on the accuracy of the PLL input source.
The most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate, to generate the CPU and system
clocks up to the device’s maximum frequency.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO, or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low power modes.
6.1.1.4 Internal Low-Speed Oscillator
The ILO provides clock frequencies for low power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The 1 KHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW). The central
timewheel is a 1 kHz, free running, 13-bit counter clocked by the
ILO. The central timewheel is always enabled except in
hibernate mode and when the CPU is stopped during debug on
chip mode. It can be used to generate periodic interrupts for
timing purposes or to wake the system from a low power mode.
Firmware can reset the central timewheel.
The central timewheel can be programmed to wake the system
periodically and optionally issue an interrupt. This enables
flexible, periodic wakeups from low power modes or coarse
timing applications. Systems that require accurate timing should
use the RTC capability instead of the central timewheel.
The 100 KHz clock (CLK100K) works as a low power system
clock to run the CPU. It can also generate time intervals such as
fast sleep intervals using the fast timewheel.
The fast timewheel is a 100 KHz, 5-bit counter clocked by the
ILO that can also be used to wake the system. The fast
timewheel settings are programmable, and the counter
automatically resets when the terminal count is reached. This
enables flexible, periodic wakeups of the CPU at a higher rate
than is allowed using the central timewheel. The fast timewheel
can generate an optional interrupt each time the terminal count
is reached.
The 33 KHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768 KHz ECO clock with no need for a crystal.
6.1.2 Internal Oscillators
6.1.2.1 MHz External Crystal Oscillator
The MHzECO provides high frequency, high precision clocking
using an external crystal (see
variety of crystal types, in the range of 4 to 25 MHz. When used
in conjunction with the PLL, it can generate CPU and system
clocks up to the device's maximum frequency (see
Phase-Locked Loop on page
the external crystal and capacitors are fixed. If a crystal is not
Document Number: 001-66235 Rev. *A
19). The GPIO pins connecting to
Figure
6-2). It supports a wide
PRELIMINARY
used then Xi must be shorted to ground and Xo must be left
floating. MHzECO accuracy depends on the crystal chosen.
Figure 6-2. MHzECO Block Diagram
6.1.2.2 32.768 kHz ECO
The 32.768 KHz external crystal oscillator (32kHzECO) provides
precision timing with minimal power consumption using an
external 32.768 KHz watch crystal (see
32kHzECO also connects directly to the sleep timer and provides
the source for the RTC. The RTC uses a 1 second interrupt to
implement the RTC functionality in firmware. The oscillator works
in two distinct power modes. This allows users to trade off power
consumption with noise immunity from neighboring circuits. The
GPIO pins connected to the external crystal and capacitors are
fixed.
Figure 6-3. 32kHzECO Block Diagram
6.1.2.3 Digital System Interconnect
The DSI provides routing for clocks taken from external clock
oscillators connected to I/O. The oscillators can also be
generated within the device in the digital system and UDBs.
While the primary DSI clock input provides access to all clocking
resources, up to eight other DSI clocks (internally or externally
Components
Components
External
External
(Pin P15[3])
PSoC
Xi
Xi
Crystal Osc
®
Crystal Osc
4 - 25 MHz
32 kHz
5: CY8C55 Family Datasheet
(Pin P15[2])
32 kHz
crystal
Capacitors
4 – 25 MHz
Xo
Capacitors
XCLK32K
crystal
XCLK_ MHZ
Xo
Figure
6-3). The
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