CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 49

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

8.2.2.2 Continuous
Continuous sample mode is used to take multiple successive
samples of a single input signal. Multiplexing multiple inputs
should not be done with this mode. There is a latency of three
conversion times before the first conversion result is available.
This is the time required to prime the decimator. After the first
result, successive conversions are available at the selected
sample rate.
8.2.2.3 Multi Sample
Multi sample mode is similar to continuous mode except that the
ADC is reset between samples. This mode is useful when the
input is switched between multiple signals. The decimator is
re-primed between each sample so that previous samples do not
affect the current conversion. Upon completion of a sample, the
next sample is automatically initiated. The results can be
transferred using either firmware polling, interrupt, or DMA.
8.2.2.4 Multi Sample (Turbo)
The multi sample (turbo) mode operates identical to the
Multi-sample mode for resolutions of 8 to 16 bits. For resolutions
of 17 to 20 bits, the performance is about four times faster than
the multi sample mode, because the ADC is only reset once at
the end of conversion.
More information on output formats is provided in the Technical
Reference Manual.
8.2.3 Start of Conversion Input
The SoC signal is used to start an ADC conversion. A digital
clock or UDB output can be used to drive this input. It can be
used when the sampling period must be longer than the ADC
conversion time or when the ADC must be synchronized to other
hardware. This signal is optional and does not need to be
connected if ADC is running in a continuous mode.
8.3 Successive Approximation ADC
The CY8C55 family of devices has two Successive
Approximation (SAR) ADCs. These ADCs are 12-bit at up to 1
Msps, with single-ended or differential inputs, making them
useful for a wide variety of sampling and control applications.
8.3.1 Functional Description
In a SAR ADC an analog input signal is sampled and compared
with the output of a DAC. A binary search algorithm is applied to
the DAC and used to determine the output bits in succession
from MSB to LSB. A block diagram of one SAR ADC is shown in
Figure
Document Number: 001-66235 Rev. *A
8-6.
PRELIMINARY
Figure 8-6. SAR ADC Block Diagram
The input is connected to the analog globals and muxes. The
frequency of the clock is 16 times the sample rate; the maximum
clock rate is 16 MHz.
8.3.2 Conversion Signals
Writing a start bit or assertion of a start of frame (SOF) signal is
used to start a conversion. SOF can be used in applications
where the sampling period is longer than the conversion time, or
when the ADC needs to be synchronized to other hardware. This
signal is optional and does not need to be connected if the SAR
ADC is running in a continuous mode. A digital clock or UDB
output can be used to drive this input. When the SAR is first
powered up or awakened from any of the sleeping modes, there
is a power up wait time of 10 µs before it is ready to start the first
conversion.
When the conversion is complete, a status bit is set and the
output signal end of frame (EOF) asserts and remains asserted
until the value is read by either the DMA controller or the CPU.
The EOF signal may be used to trigger an interrupt or a DMA
request.
8.3.3 Operational Modes
A ONE_SHOT control bit is used to set the SAR ADC conversion
mode to either continuous or one conversion per SOF signal.
DMA transfer of continuous samples, without CPU intervention,
is supported.
8.4 Comparators
The CY8C55 family of devices contains four comparators.
Comparators have these features:
■
■
■
■
■
■
vrefp
GROUND
vrefn
POWER
Input offset factory trimmed to less than 5 mV
Rail-to-rail common mode input range (V
Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low power
Comparator outputs can be routed to look up tables to perform
simple logic functions and can also be routed to digital blocks
The positive input of the comparators may be optionally passed
through a low pass filter. Two filters are provided
Comparator inputs can be connections to GPIO, DAC outputs
and SC block outputs
vin
PSoC
filtering
power
®
array
S/H
DAC
5: CY8C55 Family Datasheet
vrefp
vrefn
autozero
reset
clock
comparator
clock
SSA
digital
SAR
to V
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