CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 9

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin for
high-current DACs (IDAC).
OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out. High
current output of uncommitted opamp.
Extref0, Extref1. External reference input to the analog system.
OpAmp0-, OpAmp1-, OpAmp2-, OpAmp3-. Inverting input to
uncommitted opamp.
OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+. Noninverting
input to uncommitted opamp.
GPIO. Provides interfaces to the CPU, digital peripherals,
analog peripherals, interrupts, LCD segment drive, and
CapSense.
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 KHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillator
pin. If a crystal is not used, then Xi must be shorted to ground
and Xo must be left floating.
SIO. Provides interfaces to the CPU, digital peripherals and
interrupts with a programmable high threshold voltage, analog
comparator, high sink current, and high impedance state when
the device is unpowered.
SWDCK. SWD Clock programming and debug port connection.
SWDIO. SWD Input and Output programming and debug port
connection.
SWV. SWV output.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from V
Document Number: 001-66235 Rev. *A
Note
6. GPIOs with opamp outputs are not recommended for use with CapSense.
[6]
Figure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
Plane
Vssd
[6]
PRELIMINARY
Vddd
DDD
instead
Vssd
of from a V
USB.
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from V
of from a V
V
V
V
Requires a 1 µF capacitor to V
external use.
V
The two V
between them as short as possible, and a 1 µF capacitor to V
see
external use.
V
regulator. V
device. All other supply pins must be less than or equal to
V
V
V
V
V
V
V
V
and must be less than or equal to V
XRES. External reset pin. Active low with internal pull-up.
BOOST
BAT
CCA
CCD
DDA
DDA
DDD
DDD
SSA
SSB
SSD
DDIO0
DDIO
PSoC
Vssa
6.2 Power System on page
. Battery supply to boost pump.
. Ground for all analog peripherals.
. Ground connection for boost pump.
. Ground for all digital logic and I/O pins.
. Output of analog core regulator and input to analog core.
. Output of digital core regulator and input to digital core.
. Supply for all analog peripherals and analog core
.
. Supply for all digital peripherals and digital core regulator.
must be less than or equal to V
must be tied to a valid operating voltage (2.7 V to 5.5 V),
, V
. Power sense connection to boost pump.
Vdda
DDIO1
CCD
DDIO
DDIO
DDA
®
pins must be shorted together, with the trace
. Pins are Do Not Use (DNU) on devices without
, V
. Pins are DNU on devices without USB.
5: CY8C55 Family Datasheet
must be the highest voltage present on the
DDIO2
Plane
Vssa
, V
DDIO3
SSA
. Supply for I/O pins. Each
21. Regulator output not for
. Regulator output not for
DDA
DDA
.
.
Page 9 of 114
DDD
instead
SSD
;
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