CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 19

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

Table 6-1. Oscillator Summary
6.1.1 Internal Oscillators
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±4% accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±4% at 3 MHz, up to ±10% at 62 MHz. The
IMO, in conjunction with the PLL, allows generation of CPU and
system clocks up to the device's maximum frequency (see
Clock Domain on page
3, 6, 12, 24, 48, and 62 MHz.
Document Number: 001-66235 Rev. *A
MHzECO
kHzECO
Source
Doubler
IMO
DSI
PLL
ILO
7
24 MHz
48 MHz
32 kHz
3 MHz
4 MHz
0 MHz
1 kHz
Fmin
3-24 MHz
IMO
21). The IMO provides clock outputs at
Doubler for
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
48 MHz
USB
±4% over voltage and temperature
Crystal dependent
Input dependent
Input dependent
Input dependent
–50%, +100%
Crystal dependent
4-25 MHz
ECO
Tolerance at Fmin
24-40 MHz
PLL
PRELIMINARY
Figure 6-1. Clocking Subsystem
External IO
0-40 MHz
or DSI
Clock Mux
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
USB
System
32 kHz ECO
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works at input frequency of 24 MHz,
providing 48 MHz for the USB. It can be configured to use a clock
from the IMO, MHzECO, or the DSI (external pin).
6.1.1.3 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
PSoC
100 kHz
62 MHz
25 MHz
66 MHz
67 MHz
48 MHz
32 kHz
Fmax
1,33,100 kHz
®
ILO
±10%
Crystal dependent
Input dependent
Input dependent
Input dependent
–55%, +100%
Crystal dependent
5: CY8C55 Family Datasheet
Tolerance at Fmax
7
Bus Clock Divider
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
16 bit
w
w
w
w
s
k
e
s
k
e
s
k
e
s
k
e
10 µs max
5 ms typ, max is
crystal dependent
Input dependent
250 µs max
1 µs max
15 ms max in lowest
power mode
500 ms typ, max is
crystal dependent
Clock
Startup Time
CPU
Clock
Bus
Page 19 of 114
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