CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 31

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

6.4.11 Adjustable Output Level
This section applies only to SIO pins. SIO port pins support the
ability to provide a regulated high output level for interface to
external signals that are lower in voltage than the SIO’s
respective V
either the standard V
based on an internally generated reference. Typically a voltage
DAC (VDAC) is used to generate the reference (see
6-12). The
use and reference routing to the SIO pins. Resistive pull-up and
pull-down drive modes are not available with SIO in regulated
output mode.
6.4.12 Adjustable Input Level
This section applies only to SIO pins. SIO pins by default support
the standard CMOS and LVTTL input levels but also support a
differential mode with programmable levels. SIO pins are
grouped into pairs. Each pair shares a reference generator block
which, is used to set the digital input buffer reference level for
interface to external signals that differ in voltage from V
reference sets the pins voltage threshold for a high logic level
(see
■
■
■
■
Typically a voltage DAC (VDAC) generates the V
“DAC”
reference routing to the SIO pins.
Figure 6-12. SIO Reference for Input and Output
Document Number: 001-66235 Rev. *A
0.5 × V
0.4 × V
0.5 × V
V
REF
Input Path
Output Path
Figure
Output
Digital
Digital
section on page 53 has more details on VDAC use and
Input
SIO_Ref
DDIO
DDIO
REF
“DAC”
6-12). Available input thresholds are:
DDIO
. SIO pins are individually configurable to output
section on page 53 has more details on VDAC
Drive
Logic
DDIO
level or the regulated output, which is
Reference
Generator
Driver
Vhigh
Voutref
Vinref
PRELIMINARY
REF
Figure
reference.
DDIO
. The
PIN
6.4.13 SIO as Comparator
This section applies only to SIO pins. The adjustable input level
feature of the SIOs as explained in the
Level
threshold for the comparator is provided by the SIO's reference
generator. The reference generator has the option to set the
analog signal routed through the analog global line as threshold
for the comparator. Note that a pair of SIO pins share the same
threshold.
The digital input path in
functionality. In the figure, ‘Reference level’ is the analog signal
routed through the analog global. The hysteresis feature can
also be enabled for the input buffer of the SIO, which increases
noise immunity for the comparator.
6.4.14 Hot Swap
This section applies only to SIO pins. SIO pins support ‘hot swap’
capability to plug into an application without loading the signals
that are connected to the SIO pins even when no power is
applied to the PSoC device. This allows the unpowered PSoC to
maintain a high impedance load to the external device while also
preventing the PSoC from being powered through a GPIO pin’s
protection diode.
6.4.15 Over Voltage Tolerance
All I/O pins provide an over voltage (V
tolerance feature at any operating V
■
■
■
A common application for this feature is connection to a bus such
as I
voltages. In the I
Open Drain, Drives Low mode for the SIO pin. This allows an
external pull-up to pull the I
supply. For example, the PSoC chip could operate at 2.7 V, and
an external device could run from 5 V. Note that the SIO pin’s V
and V
pin.
The I/O pin must be configured into a high impedance drive
mode, open drain low drive mode, or pull-down drive mode, for
over voltage tolerance to work properly. Absolute maximum
ratings for the device must be observed for all I/O pins.
6.4.16 Reset Configuration
At reset, all I/Os are reset to the High Impedance Analog state.
6.4.17 Low Power Functionality
In all low power modes the I/O pins retain their state until the part
is awakened and changed or reset. To awaken the part, use a
pin interrupt, because the port interrupt logic continues to
function in all low power modes.
There are no current limitations for the SIO pins as they present
a high impedance load to the external circuit.
The GPIO pins must be limited to 100 µA using a current limiting
resistor. GPIO pins clamp the pin voltage to approximately one
diode above the V
In case of a GPIO pin configured for analog input/output, the
analog voltage on the pin must not exceed the V
voltage to which the GPIO belongs.
PSoC
2
C where different devices are running from different supply
section can be used to construct a comparator. The
IL
levels are determined by the associated V
®
5: CY8C55 Family Datasheet
2
C case, the PSoC chip is configured into the
DDIO
Figure 6-9 on page 28
supply.
2
C bus voltage above the PSoC pin
DD
DDIO
.
6.4.12 Adjustable Input
< V
IN
illustrates this
Page 31 of 114
< V
DDIO
DDIO
DDA
supply
supply
)
IH
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