CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 60

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

11.2 Device Level Specifications
Specifications are valid for –40 °C ≤ T
where noted.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Document Number: 001-66235 Rev. *A
Notes
V
V
V
V
V
V
V
I
13. The power supplies can be brought up in any sequence however once stable Vdda must be greater than or equal to all other supplies.
14. The V
15. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
16. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
Parameter
DD
DDA
DDA
DDD
DDD
DDIO
CCA
CCD
[15]
PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device data sheet and component datasheets.
[14]
DDIO
supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ V
Analog supply voltage and input to analog core
regulator
Analog supply voltage, analog regulator bypassed Analog core regulator disabled
Digital supply voltage relative to V
Digital supply voltage, digital regulator bypassed
I/O supply voltage relative to V
Direct analog core voltage input (Analog regulator
bypass)
Direct digital core voltage input (Digital regulator
bypass)
Active Mode, V
Execute from Flash cache, see
on page 11
Sleep Mode
CPU = OFF
RTC = ON (= ECO32K ON, in low power mode)
Sleep timer = ON (= ILO ON at 1 kHz)
WDT = OFF
POR = ON
Boost = OFF
SIO pins in single ended input, unregulated output
mode
Hibernate Mode
Hibernate mode current
All regulators and oscillators off.
SRAM retention
GPIO interrupts are active
Boost = OFF
SIO pins in single ended input, unregulated output
mode
and
[16]
Flash Program Memory on page 16
DD
Description
= 2.7 V–5.5 V
A
≤ 85 °C and T
SSIO
Cache Controller
SSD
PRELIMINARY
J
≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
Analog core regulator enabled
Digital core regulator enabled
Digital core regulator disabled
Analog core regulator disabled
Digital core regulator disabled
CPU at 6 MHz
V
V
V
V
DD
DD
DD
DD
= V
= V
= V
= V
DDIO
DDIO
DDIO
DDIO
= 4.5–5.5 V
= 2.7–3.6 V
= 4.5–5.5 V
= 2.7–3.6 V
PSoC
Conditions
®
5: CY8C55 Family Datasheet
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
1.71
1.71
1.71
1.71
Min
2.7
2.7
2.7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1000
Typ
1.8
1.8
1.8
1.8
–
–
–
–
5
–
–
–
–
–
3
–
–
–
–
–
–
Page 60 of 114
V
V
DDA
DDA
Max
1.89
1.89
1.89
1.89
5.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DDIO
[13]
[13]
≤ V
Units
mA
mA
mA
µA
µA
µA
µA
µA
µA
nA
nA
nA
nA
nA
nA
DDA
V
V
V
V
V
V
V
.
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