CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 17

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

5.5 Memory Map
The Cortex-M3 has a fixed address map, which allows
peripherals to be accessed by simple memory access
instructions.
5.5.1 Address Map
The 4-GB address space is divided into the ranges shown in
Table
Table 5-2. Address Map
Table 5-3. Peripheral Data Address Map
Document Number: 001-66235 Rev. *A
0x00000000 –
0x1FFFFFFF
0x20000000 –
0x3FFFFFFF
0x40000000 –
0x5FFFFFFF
0x60000000 –
0x9FFFFFFF
0xA0000000 –
0xDFFFFFFF
0xE0000000 –
0xFFFFFFFF
0x00000000 – 0x0003FFFF 256 KB flash
0x1FFF8000 – 0x1FFFFFFF 32 KB SRAM in Code region
0x20000000 – 0x20007FFF 32 KB SRAM in SRAM region
0x40004000 – 0x400042FF Clocking, PLLs, and oscillators
0x40004300 – 0x400043FF Power management
0x40004500 – 0x400045FF Ports interrupt control
0x40004700 – 0x400047FF Flash programming interface
0x40004800 – 0x400048FF Cache controller
Address Range
5-2:
Address Range
0.5 GB
0.5 GB
0.5 GB
1 GB
1 GB
0.5 GB
Size
Program code. This includes the
exception vector table at power
up, which starts at address 0.
Static RAM. This includes a 1
MByte bit-band region starting at
0x20000000 and a 32 Mbyte
bit-band alias region starting at
0x22000000.
Peripherals. This includes a
1 MByte bit-band region starting
at 0x40000000 and a 32 Mbyte
bit-band alias region starting at
0x42000000.
External RAM.
External peripherals.
Internal peripherals, including the
NVIC and debug and trace
modules.
Purpose
PRELIMINARY
Use
Table 5-3. Peripheral Data Address Map (continued)
The bit-band feature allows individual bits in words in the
bit-band region to be read or written as atomic operations. This
is done by reading or writing bit 0 of corresponding words in the
bit-band alias region. For example, to set bit 3 in the word at
address 0x20000000, write a 1 to address 0x2200000C. To test
the value of that bit, read address 0x2200000C and the result is
either 0 or 1 depending on the value of the bit.
Most memory accesses done by the Cortex-M3 are aligned, that
is, done on word (4-byte) boundary addresses. Unaligned
accesses of words and 16-bit half-words on nonword boundary
addresses can also be done, although they are less efficient.
5.5.2 Address Map and Cortex-M3 Buses
The ICode and DCode buses are used only for accesses within
the Code address range, 0 - 0x1FFFFFFF.
The System bus is used for data accesses and debug accesses
within the ranges 0x20000000 - 0xDFFFFFFF and 0xE0100000
- 0xFFFFFFFF. Instruction fetches can also be done within the
range 0x20000000 - 0x3FFFFFFF, although these can be slower
than instruction fetches via the ICode bus.
The private peripheral bus (PPB) is used within the Cortex-M3 to
access system control registers and debug and trace module
registers.
0x40004900 – 0x400049FF I
0x40004E00 – 0x40004EFF Decimator
0x40004F00 – 0x40004FFF Fixed timer/counter/PWMs
0x40005000 – 0x400051FF I/O ports control
0x40005800 – 0x40005FFF Analog Subsystem Interface
0x40006000 – 0x400060FF USB Controller
0x40006400 – 0x40006FFF UDB Configuration
0x40007000 – 0x40007FFF PHUB Configuration
0x40008000 – 0x400087FF EEPROM
0x4000A000 – 0x4000A400 CAN
0x4000C000 – 0x4000C800 Digital Filter Block
0x40010000 – 0x4001FFFF Digital Interconnect Configuration
0xE0000000 – 0xE00FFFFF Cortex-M3 PPB Registers,
PSoC
Address Range
®
5: CY8C55 Family Datasheet
including NVIC, debug, and trace
2
C controller
Purpose
Page 17 of 114
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