CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 29

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

6.4.1 Drive Modes
Each GPIO and SIO pin is individually configurable into one of
the eight drive modes listed in
are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]
registers.
each of the eight drive modes.
state based on the port data register value or digital array signal
Table 6-6. Drive Modes
■
Document Number: 001-66235 Rev. *A
Note
9. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
High Impedance Analog
Diagram
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/O’s digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not
provide digital input functionality.
0
1
2
3
4
5
6
7
Figure 6-11
High impedence analog
High Impedance digital
Resistive pull-up
Resistive pull-down
Open drain, drives low
Open drain, drive high
Strong drive
Resistive pull-up and pull-down
depicts a simplified pin view based on
Drive Mode
Table
Table 6-6
[9]
0.
4.
DR
PS
DR
PS
[9]
Open Drain ,
Drives Low
6-6. Three configuration bits
High Impedance
Analog
shows the I/O pin’s drive
Pin
Pin
PRELIMINARY
[9]
1.
DR
PS
5.
DR
PS
Figure 6-11. Drive Mode
Open Drain ,
High Impedance
Drives High
Digital
PRTxDM2
Vddio
0
0
0
0
1
1
1
1
Pin
Pin
PRTxDM1
if bypass mode is selected. Note that the actual I/O pin voltage
is determined by a combination of the selected drive mode and
the load at the pin. For example, if a GPIO pin is configured for
resistive pull-up mode and driven high while the pin is floating,
the voltage measured at the pin is a high logic state. If the same
GPIO pin is externally tied to ground then the voltage
unmeasured at the pin is a low logic state.
PS
2.
DR
PS
6.
■
DR
High Impedance Digital
Strong Drive
Resistive
Pull-Up
To achieve the lowest chip current in sleep modes, all I/Os
must either be configured to the high impedance analog
mode, or have their pins driven to a power supply rail by the
PSoC device or by external circuitry.
The input buffer is enabled for digital signal input. This is the
standard high impedance (HiZ) state recommended for digital
inputs.
PSoC
0
0
1
1
0
0
1
1
Vddio
Vddio
Pin
Pin
®
PRTxDM0
5: CY8C55 Family Datasheet
PS
3.
7.
DR
DR
PS
0
1
0
1
0
1
0
1
Resistive
Pull-Up and Pull-Down
Resistive
Pull-Down
Vddio
Vddio
Res High (5K)
Res High (5K)
PRTxDR = 1
Strong High
Strong High
Strong High
Pin
Pin
High-Z
High-Z
High-Z
Page 29 of 114
Res Low (5K)
Res Low (5K)
PRTxDR = 0
Strong Low
Strong Low
Strong Low
High-Z
High-Z
High-Z
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