CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 26

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

6.4 I/O System and Routing
PSoC I/Os are extremely flexible. Every GPIO has analog and
digital I/O capability. All I/Os have a large number of drive modes,
which are set at POR. PSoC also provides up to four individual
I/O voltage domains through the V
There are two types of I/O pins on every device; those with USB
provide a third type. Both general purpose I/O (GPIO) and
special I/O (SIO) provide similar digital functionality. The primary
differences are their analog capability and drive strength.
Devices that include USB also provide two USBIO pins that
support specific USB functionality as well as limited GPIO
capability.
All I/O pins are available for use as digital inputs and outputs for
both the CPU and digital peripherals. In addition, all I/O pins can
generate an interrupt. The flexible and advanced capabilities of
the PSoC I/O, combined with any signal to any pin routability,
greatly simplify circuit design and board layout. All GPIO pins can
be used for analog input, CapSense
while SIO pins are used for voltages in excess of V
programmable output voltages.
■
Document Number: 001-66235 Rev. *A
Note
Features supported by both GPIO and SIO:
❐
❐
❐
❐
❐
❐
❐
❐
8. GPIOs with opamp outputs are not recommended for use with CapSense.
Separate I/O supplies and voltages for up to four groups of I/O
Digital peripherals use DSI to connect the pins
Input or output or both for CPU and DMA
Eight drive modes
Every pin can be an interrupt source configured as rising
edge, falling edge or both edges. If required, level sensitive
interrupts are supported through the DSI
Dedicated port interrupt vector for each port
Slew rate controlled digital output drive mode
Access port control and configuration registers on either port
basis or pin basis
DDIO
[8]
, and LCD segment drive,
pins.
PRELIMINARY
DDA
and for
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■
■
❐
❐
Additional features only provided on the GPIO pins:
❐
❐
❐
❐
❐
Additional features only provided on SIO pins:
❐
❐
❐
❐
❐
❐
USBIO features:
❐
❐
❐
❐
❐
❐
PSoC
Separate port read (PS) and write (DR) data registers to avoid
read modify write errors
Special functionality on a pin by pin basis
LCD segment drive on LCD equipped devices
CapSense on CapSense equipped devices
Analog input and output capability
Continuous 100 µA clamp current capability
Standard drive strength down to 2.7 V
Higher drive strength than GPIO
Hot swap capability (5 V tolerance at any operating V
Programmable and regulated high input and output drive
levels down to 1.2 V
No analog input or LCD capability
Over voltage tolerance up to 5.5 V
SIO can act as a general purpose analog comparator
Full speed USB 2.0 compliant I/O
Highest drive strength for general purpose use
Input, output, or both for CPU and DMA
Input, output, or both for digital peripherals
Digital output (CMOS) drive mode
Each pin can be an interrupt source configured as rising
edge, falling edge, or both edges
®
5: CY8C55 Family Datasheet
Page 26 of 114
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