CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 5

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

PSoC’s nonvolatile subsystem consists of flash and
byte-writeable EEPROM. It provides up to 256 KB of on-chip
flash. The CPU can reprogram individual blocks of flash,
enabling boot loaders. A powerful and flexible protection model
secures the user's sensitive information, allowing selective
memory block locking for read and write protection. Two KB of
byte-writable EEPROM is available on-chip to store application
data.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the V
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow V
to be set independently of V
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
make the SIO function as a general purpose analog comparator.
For devices with FS USB, the USB physical interface is also
provided (USBIO). When not using USB, these pins may also be
used for limited digital functionality and device programming. All
the features of the PSoC I/Os are covered in detail in the
System and Routing”
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the master clock base for
the system, and has one-percent accuracy at 3 MHz. The IMO
can be configured to run from 3 MHz up to 62MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 67 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low-power ILO for the sleep and watchdog timers. A
32.768 kHz external watch crystal is also supported for use in
RTC applications. The clocks, together with programmable clock
dividers, provide the flexibility to integrate most timing
requirements.
Document Number: 001-66235 Rev. *A
2
C bus where the PSoC may not be powered when
section on page 26 of this data sheet.
DDIO
when used as outputs. When
DDIO
PRELIMINARY
pins. Every GPIO
“6.4 I/O
OH
The CY8C55 family supports a wide supply operating range from
2.7 to 5.5 V. This allows operation from regulated supplies such
as 3.3 V ± 10% or 5.0 V ± 10%, or directly from a wide range of
battery types. It also provides an integrated high efficiency
synchronous boost converter that can power the device from
supply voltages as low as 1.8 V. The designer can use the boost
converter to generate other voltages required by the device,
such as a 3.3 V supply for LCD glass drive. The boost’s output
is available on the V
application to be powered from the PSoC.
PSoC supports a wide range of low power modes. These include
a 1-µA hibernate mode with RAM retention and a 3-µA sleep
mode with RTC. In the second mode, the optional 32.768 kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 2 mA when the CPU is running at
6 MHz.
The details of the PSoC power modes are covered in the
Power System”
PSoC uses a SWD interface for programming, debug, and test.
Using this standard interface enables the designer to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. The Cortex-M3 debug and trace
modules include FPB, DWT, and ITM. These modules have
many features to help solve difficult debug and trace problems.
Details of the programming, test, and debugging interfaces are
discussed in the
section on page 55 of this data sheet.
2. Pinouts
The V
by the black lines drawn on the pinout diagrams in
Figure
multiple interface voltage levels, eliminating the need for off-chip
level shifters. Each V
associated I/O pins and opamps. On the 68-pin and 100-pin
devices, each set of V
100 mA. The 48 pin device may sink up to 100 mA total for all
Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all
Vddio1 plus Vddio3 associated I/O pins.
PSoC
DDIO
2-2. Using the V
pin that supplies a particular set of pins is indicated
®
5: CY8C55 Family Datasheet
section on page 21 of this data sheet.
“Programming, Debug Interfaces, Resources”
BOOST
DDIO
DDIO
DDIO
may sink up to 100 mA total to its
pin, allowing other devices in the
associated pins may sink up to
pins, a single PSoC can support
Page 5 of 114
Figure 2-1
“6.2
and
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