CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 48

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

8.2 Delta-sigma ADC
The CY8C38 device contains one delta-sigma ADC. This ADC
offers differential input, high resolution and excellent linearity,
making it a good ADC choice for both audio signal processing
and measurement applications. The converter's nominal
operation is 16 bits at 48 ksps. The ADC can be configured to
output 20-bit resolution at data rates of up to 187 sps. At a fixed
clock rate, resolution can be traded for faster data rates as
shown in
Table 8-1. Delta-sigma ADC Performance
Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024 V
8.2.1 Functional Description
The ADC connects and configures three basic components,
input buffer, delta-sigma modulator, and decimator. The basic
block diagram is shown in
muxes is delivered to the delta-sigma modulator either directly or
through the input buffer. The delta-sigma modulator performs the
actual analog to digital conversion. The modulator over-samples
the input and generates a serial data stream output. This high
speed data stream is not useful for most applications without
some type of post processing, and so is passed to the decimator
through the Analog Interface block. The decimator converts the
high speed serial data stream into parallel ADC results. The
Document Number: 001-66235 Rev. *A
1000000
100000
10000
1000
100
10
Bits
1
20
16
12
6
8
Table 8-1
8
Continuous
Multi-Sample
Multi-SampleTurbo
Maximum Sample Rate
and
10
Figure
Figure
(sps)
192 k
384 k
12
48 k
187
8-3.
Resolution, bits
Resolution, bits
8-4. The signal from the input
14
16
PRELIMINARY
SINAD (dB)
18
84
66
43
–
20
22
modulator/decimator frequency response is [(sin x)/x]
frequency response is shown in
Figure 8-4. Delta-sigma ADC Block Diagram
Figure 8-5. Delta-sigma ADC Frequency Response, Normal-
ized to Output, Sample Rate = 48 kHz
Resolution and sample rate are controlled by the Decimator.
Data is pipelined in the decimator; the output is a function of the
last four samples. When the input multiplexer is switched, the
output data is not valid until after the fourth sample after the
switch.
8.2.2 Operational Modes
The ADC can be configured by the user to operate in one of four
modes: Single Sample, Multi Sample, Continuos, or Multi
Sample (Turbo). All four modes are started by either a write to
the start bit in a control register or an assertion of the Start of
Conversion (SoC) signal. When the conversion is complete, a
status bit is set and the output signal End of Conversion (EoC)
asserts high and remains high until the value is read by either the
DMA controller or the CPU.
8.2.2.1 Single Sample
In Single Sample mode, the ADC performs one sample
conversion on a trigger. In this mode, the ADC stays in standby
state waiting for the SoC signal to be asserted. When SoC is
signaled the ADC performs four successive conversions. The
first three conversions prime the decimator. The ADC result is
valid and available after the fourth conversion, at which time the
EoC signal is generated. To detect the end of conversion, the
system may poll a control register for status. When the transfer
is done the ADC reenters the standby state where it stays until
another SoC event.
(Analog Routing)
PSoC
Input Mux
Input Mux
Negative
-100
Positive
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
100
®
5: CY8C55 Family Datasheet
1,000
Buffer
Input
Input frequency, Hz
Input Frequency, Hz
Modulator
Figure
10,000
Sigma
Delta
8-5.
Decimator
100,000
Page 48 of 114
SOC
4
; a typical
12 to 20 Bit
Result
EOC
1,000,000
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