CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 10

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

4. CPU
4.1 ARM Cortex-M3 CPU
The CY8C55 family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low-power 32-bit three-stage pipelined
Harvard-architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt
handling features.
The Cortex-M3 CPU subsystem includes these features:
■
■
■
■
■
■
■
Document Number: 001-66235 Rev. *A
ARM Cortex-M3 CPU
Programmable nested vectored interrupt controller (NVIC),
tightly integrated with the CPU core
Full featured debug and trace module, tightly integrated with
the CPU core
Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB
of SRAM
Cache controller
Peripheral HUB (PHUB)
DMA controller
SRAM
SRAM
32 KB
32 KB
Interrupt Inputs
SWD
Bus
Matrix
Bus
Matrix
Debug Block
AHB Spokes
Controller
Vectored
Interrupt
Nested
(NVIC)
(SWD)
GPIO
Flash Patch and
Breakpoint
AHB
I- Bus
(FPB)
Figure 4-1. ARM Cortex-M3 Block Diagram
AHB Bridge and Bus Matrix
PRELIMINARY
C-Bus
D-Bus
AHB
Digital
Prog.
Peripherals
PHUB
AHB
S-Bus
Cortex M3 Wrapper
Cortex M3 CPU Core
4.1.1 Cortex-M3 Features
The Cortex-M3 CPU features include:
■
■
Analog
Prog.
4 GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and
simultaneous accesses of instructions, data, and peripherals.
The Thumb
performance at Thumb-level code density. This includes 16-bit
and 32-bit instructions. Advanced instructions include:
❐
❐
❐
❐
❐
❐
❐
PSoC
Bit-field control
Hardware multiply and divide
Saturation
If-Then
Wait for events and interrupts
Exclusive access and barrier
Special register access
DMA
®
®
-2 instruction set, which offers ARM-level
5: CY8C55 Family Datasheet
Bus
Matrix
Functions
Special
Cache
Instrumentation
Watchpoint and
Trace Module
Interface Unit
Trace (DWT)
Trace Port
(TPIU)
(ITM)
Data
256 KB
Flash
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