CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 54

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

8.10.1 Current DAC
The current DAC (IDAC) can be configured for the ranges 0 to
32 µA, 0 to 256 µA, and 0 to 2.04 mA. The IDAC can be
configured to source or sink current.
8.10.2 Voltage DAC
For the voltage DAC (VDAC), the current DAC output is routed
through resistors. The two ranges available for the VDAC are 0
to 1.024 V and 0 to 4.096 V. In voltage mode any load connected
to the output of a DAC should be purely capacitive (the output of
the VDAC is not buffered).
8.11 Up/Down Mixer
In continuous time mode, the SC/CT block components are used
to build an up or down mixer. Any mixing application contains an
input signal frequency and a local oscillator frequency. The
polarity of the clock, Fclk, switches the amplifier between
inverting or noninverting gain. The output is the product of the
input and the switching function from the local oscillator, with
frequency components at the local oscillator plus and minus the
signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level
frequency components at odd integer multiples of the local
oscillator frequency. The local oscillator frequency is provided by
the selected clock source for the mixer.
Continuous time up and down mixing works for applications with
input signals and local oscillator frequencies up to 1 MHz.
Figure 8-14. Mixer Configuration
Document Number: 001-66235 Rev. *A
sc_clk
Vin
Vref
R
mix
0 20 k or 40 k
0
1
Reference
C2 = 1.7 pF
C1 = 850 fF
Source
R
mix
sc_clk
0 20 k or 40 k
PRELIMINARY
Figure 8-13. DAC Block Diagram
Scaler
Vout
I
I
8.12 Sample and Hold
The main application for a sample and hold, is to hold a value
stable while an ADC is performing a conversion. Some
applications require multiple signals to be sampled
simultaneously, such as for power calculations (V and I).
Figure 8-15. Sample and Hold Topology
(Φ1 and Φ2 are opposite phases of a clock)
8.12.1 Down Mixer
The S+H can be used as a mixer to down convert an input signal.
This circuit is a high bandwidth passive sample network that can
sample input signals up to 14 MHz. This sampled value is then
held using the opamp with a maximum clock rate of 4 MHz. The
output frequency is at the difference between the input frequency
and the highest integer multiple of the Local Oscillator that is less
than the input.
8.12.2 First Order Modulator - SC Mode
A first order modulator is constructed by placing the switched
capacitor block in an integrator mode and using a comparator to
provide a 1-bit feedback to the input. Depending on this bit, a
reference voltage is either subtracted or added to the input
signal. The block output is the output of the comparator and not
the integrator in the modulator case. The signal is downshifted
and buffered and then processed by a decimator to make a
delta-sigma converter or a counter to make an incremental
converter. The accuracy of the sampled data from the first-order
modulator is determined from several factors. The main
application for this modulator is for a low frequency ADC with
high accuracy. Applications include strain gauges,
thermocouples, precision voltage, and current measurement.
1x , 8x , 64x
1x , 8x , 64x
source
V
V
sink
n
i
ref
PSoC
Range
Range
3R
R
Φ
Φ
Φ
Φ
2
2
1
1
®
5: CY8C55 Family Datasheet
Vout
C
C
1
3
Φ
Φ
Φ
Φ
2
1
2
1
Iout
C
C
2
4
Φ
Φ
Φ
Φ
1
2
1
2
V
V
ref
ref
V
out
Page 54 of 114
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