CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 4

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

Figure 1-1
family. They are:
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PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power UDBs. PSoC Creator provides a library of pre-built and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. The designer can also easily create a digital
circuit using boolean primitives by means of graphical design
entry. Each UDB contains programmable array logic
(PAL)/programmable logic device (PLD) functionality, together
with a small state machine engine to support a wide variety of
peripherals.
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C55 family, these blocks can include four 16-bit timers,
counters, and PWM blocks; I
Full-Speed USB; and Full CAN 2.0b.
For more details on the peripherals see the
Peripherals”
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem”
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 1% error over
temperature and voltage. The configurable analog subsystem
includes:
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Document Number: 001-66235 Rev. *A
ARM Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
Analog muxes
Comparators
Analog mixers
Voltage references
ADCs
DACs
Digital filter block (DFB)
illustrates the major components of the CY8C55
section on page 32 of this data sheet. For
section on page 32 of this data sheet.
2
C slave, master, and multimaster;
“Example
PRELIMINARY
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. One of the ADCs in the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features:
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This converter addresses a wide variety of precision analog
applications including some of the most demanding sensors.
The CY8C55 family also offers up to two SAR ADCs. Featuring
12-bit conversions at up to 1 M samples per second, they also
offer low nonlinearity and offset errors and SNR better than
70 dB. They are well-suited for a variety of higher speed analog
applications.
The output of any of the ADCs can optionally feed the
programmable DFB via DMA without CPU intervention. The
designer can configure the DFB to perform IIR and FIR digital
filters and several user defined custom functions. The DFB can
implement filters with up to 64 taps. It can perform a 48-bit
multiply-accumulate (MAC) operation in one clock cycle.
Four high-speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
DAC outputs using the UDB array. This can be used to create a
pulse width modulated (PWM) DAC of up to 10 bits, at up to
48 kHz. The digital DACs in each UDB support PWM, PRS, or
delta-sigma algorithms with programmable widths.
In addition to the ADCs, DACs, and DFB, the analog subsystem
provides multiple:
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See the
sheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 67 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
Less than 0.5 mV offset
A gain error of 0.2%
Integral non linearity (INL) less than ±2 LSB
Differential non linearity (DNL) less than ±1 LSB
SINAD better than 84 dB in 16-bit mode
Comparators
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
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PSoC
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
“Analog Subsystem”
®
5: CY8C55 Family Datasheet
section on page 44 of this data
Page 4 of 114
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