CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 43

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

The Timer/Counter/PWM peripheral can select from multiple
clock sources, with input and output signals connected through
the DSI routing. DSI routing allows input and output connections
to any device pin and any internal digital signal accessible
through the DSI. Each of the four instances has a compare
output, terminal count output (optional complementary compare
output), and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
Timer/Counter/PWM features include:
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■
■
■
■
■
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■
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Figure 7-21. Timer/Counter/PWM
Document Number: 001-66235 Rev. *A
SDA
SCL
16-bit timer/counter/PWM (down count only)
Selectable clock source
PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
Period reload on start, reset, and terminal count
Interrupt on terminal count, compare true, or capture
Dynamic counter reads
Timer capture mode
Count while enable signal is asserted mode
Free run mode
One-shot mode (stop at end of period)
Complementary PWM outputs with deadband
PWM output kill
Clock
Reset
Enable
Capture
Kill
Condition
START
Timer / Counter /
PWM 16-bit
ADDRESS
1 - 7
R/W
8
IRQ
TC / Compare!
Compare
Figure 7-22. I
ACK
9
PRELIMINARY
2
1 - 7
C Complete Transfer Timing
DATA
7.8 I
The I
designed to interface the PSoC device with a two wire I
communication bus. The bus is compliant with Philips ‘The I
Specification’ version 2.1. Additional I
instantiated using Universal Digital Blocks (UDBs) in PSoC
Creator, as required.
To eliminate the need for excessive CPU intervention and
overhead, I
and generation of framing bits. I
or multimaster (Slave and Master). In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I
DSI routing and allows direct connections to any GPIO or SIO
pins.
I
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■
■
■
■
Data transfers follow the format shown in
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
2
C features include:
8
Slave and Master, Transmitter, and Receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
7 or 10-bit addressing (10-bit addressing requires firmware
support)
SMBus operation (through firmware support - SMBus
supported in hardware in UDBs)
PSoC
2
2
C peripheral provides a synchronous two wire interface
C
ACK
9
2
C specific support is provided for status detection
®
5: CY8C55 Family Datasheet
1 - 7
DATA
2
C operates as a slave, a master,
8
2
2
C interfaces can be
C interfaces through the
Figure
ACK
9
Page 43 of 114
7-22. After the
2
Condition
C serial
STOP
2
C
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