CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 25

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

6.3 Reset
CY8C55 has multiple internal and external reset sources
available. The reset sources are:
■
■
■
■
Figure 6-7. Resets
The term system reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register holds the source of the most recent reset
or power voltage monitoring interrupt. The program may
examine this register to detect and report exception conditions.
This register is cleared after a power on reset.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
■
Document Number: 001-66235 Rev. *A
Power source monitoring - The analog and digital power
voltages, V
several different modes during power up, active mode, and
sleep mode (buzzing). If any of the voltages goes outside
predetermined ranges then a reset is generated. The monitors
are programmable to generate an interrupt to the processor
under certain conditions before reaching the reset thresholds.
External - The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull-up to Vddio1. V
have voltage applied before the part comes out of reset.
Watchdog timer - A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset. The watchdog timer should not be used
during sleep and hibernate modes.
Software - The device can be reset under program control.
Reset
IPOR - Initial Power on Reset
Pin
At initial power on, IPOR monitors the power voltages V
and V
corresponding internal regulators. The trip level is not precise.
It is set to approximately 1 volt, which is below the lowest
specified operating voltage but high enough for the internal
DDA
Vddd Vdda
, both directly at the pins and at the outputs of the
Watchdog
DDA
Software
Monitors
Register
External
Voltage
Power
Reset
Timer
Reset
Level
, V
DDD
, V
CCA
DDD
, and V
Controller
, V
Reset
DDA
CCD
, and Vddio1 must all
are monitored in
PRELIMINARY
System
Processor
Reset
Interrupt
DDD
■
Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High
Voltage Interrupt
6.3.1.2 Other Reset Sources
■
■
■
Interrupt Supply
ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog
High Voltage Interrupt
XRES - External Reset
SRES - Software Reset
WRES - Watchdog Timer Reset
AHVI
circuits to be reset and to hold their reset state. The monitor
generates a reset pulse that is at least 100 ns wide. It may be
much wider if one or more of the voltages ramps up slowly.
To save power the IPOR circuit is disabled when the internal
digital supply is stable. When the voltage is high enough, the
IMO starts.
Interrupt circuits are available to detect when V
go outside a voltage range. For AHVI, V
fixed trip level. For ALVI and DLVI, V
compared to trip levels that are programmable, as listed in
Table
a device reset instead of an interrupt.
DLVI
ALVI
The monitors are disabled until after IPOR. During sleep
mode these circuits are periodically activated (buzzed). If an
interrupt occurs during buzzing then the system first enters its
wakeup sequence. The interrupt is then recognized and may
be serviced.
CY8C55 has a dedicated XRES pin which holds the part in
reset while held active (low). The response to an XRES is the
same as to an IPOR reset. The external reset is active low. It
includes an internal pull-up resistor. XRES is active during
sleep and hibernate modes.
A reset can be commanded under program control by setting
a bit in the software reset register. This is done either directly
by the program or indirectly by DMA access. The response to
a SRES is the same as after an IPOR reset.
Another register bit exists to disable this function.
The watchdog reset detects when the software program is no
longer being executed correctly. To indicate to the watchdog
timer that it is running correctly, the program must periodically
reset the timer. If the timer is not reset before a user-specified
amount of time, then a reset is generated.
Note IPOR disables the watchdog function. The program
must enable the watchdog function at an appropriate point in
the code by setting a register bit. When this bit is set, it cannot
be cleared again except by an IPOR power on reset event.
The watchdog timer should not be used if the device is to be
put into sleep or hibernate mode.
PSoC
6-5. ALVI and DLVI can also be configured to generate
®
V
V
V
DDD
DDA
DDA
5: CY8C55 Family Datasheet
2.7 V-5.5 V 2.71 V-5.45 V in
2.7 V-5.5 V 2.71 V-5.45 V in
2.7 V-5.5 V 5.75 V
Normal
Voltage
Range
250 mV
increments
250 mV
increments
Available Trip
Settings
DDA
DDA
is compared to a
Page 25 of 114
and V
DDA
Accuracy
and V
DDD
±2%
±2%
±2%
DDD
are
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