NAND512R3A2CZA6E Micron Technology Inc, NAND512R3A2CZA6E Datasheet - Page 14

• Manufacturer Part Number: NAND512R3A2CZA6E
• Manufacturer: Micron Technology Inc

Specifications of NAND512R3A2CZA6E

• Cell Type: NAND
• Density: 512Mb
• Access Time (max): 15us
• Interface Type: Parallel
• Address Bus: 26b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.95V
• Word Size: 8b
• Number Of Words: 64M
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / Rohs Status: Compliant

Signal descriptions
3
3.1
3.2
3.3
3.4
3.5
14/55
Signal descriptions
See
connected to this device.
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used to input the selected address, output the data during a read
operation or input a command or data during a write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They are used to output the data
during a read operation or input data during a write operation. Command and address
inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and read
circuitry. When Chip Enable is Low, V
If Chip Enable goes High (V
remains selected and does not go into standby mode.
While the device is busy reading:
Figure 1: Logic
the Chip Enable input should be held Low during the whole busy time (t
devices that do not feature the Chip Enable don’t care option. Otherwise, the read
operation in progress is interrupted and the device goes into standby mode.
for devices that feature the Chip Enable don’t care option, the Chip Enable going High
during the busy time (t
go into standby mode.
diagram, and
BLBH1
IH
) while the device is busy programming or erasing, the device
) will not interrupt the read operation and the device will not
Table 3: Signal
IL
, the device is selected.
names, for a brief overview of the signals
NAND512-A2C
BLBH1
) for