NAND512R3A2CZA6E Micron Technology Inc, NAND512R3A2CZA6E Datasheet - Page 32

• Manufacturer Part Number: NAND512R3A2CZA6E
• Manufacturer: Micron Technology Inc

Specifications of NAND512R3A2CZA6E

• Cell Type: NAND
• Density: 512Mb
• Access Time (max): 15us
• Interface Type: Parallel
• Address Bus: 26b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.95V
• Word Size: 8b
• Number Of Words: 64M
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / Rohs Status: Compliant

Software algorithms
7.3
7.4
7.5
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Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
Figure
Figure 17. Garbage collection
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm not all blocks get used at the same
rate.
The wear-leveling algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leveling levels:
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
Error correction code
An error correction code (ECC) can be implemented in the NAND flash memories to identify
and correct errors in the data.
For every 2048 bits in the device the implementation of 22 bits of ECC (16 bits for line parity
plus 6 bits for column parity) is required.
First level wear-leveling, new data is programmed to the free blocks that have had the
fewest write cycles
Second level wear-leveling, long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
17).
Invalid
Valid
page
page
Old area
(erased)
Free
page
New area (after GC)
AI07599B
NAND512-A2C