ST52T430K3M6 STMicroelectronics, ST52T430K3M6 Datasheet - Page 13

• Manufacturer Part Number: ST52T430K3M6
• Manufacturer: STMicroelectronics

Specifications of ST52T430K3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/UART
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5/5.8V
• Operating Supply Voltage (min): 2.7/3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 34
• Package Type: SSO
• Lead Free Status / Rohs Status: Not Compliant

The ST52x430 core uses flags that correspond to
the actual mode. As soon as an interrupt is
generated the ST52x430 core uses the interrupt
flags instead of the normal flags.
Each interrupt level has its own set of flags, which
is saved in the STACK together with the Program
Counter. These flags are restored from the STACK
automatically when a RETI instruction is executed.
If the MCU was in normal mode before an interrupt,
the normal flags are restored when the RETI
instruction is executed.
Note: A CALL subroutine is a normal mode
execution. For this reason, a RET instruction,
consequent to a CALL instruction does not affect
the normal mode set of flags.
Flags are not cleared during context switching and
remain in the state they were at the end of the last
interrupt routine switching.
The Carry flag is set when an overflow occurs
during arithmetic operations, otherwise it
cleared.
The Sign flag is set when an underflow occurs
during arithmetic operations, otherwise it is
cleared.
2.3 Address Spaces
ST52x430 has four separate address spaces:
I
Figure 2.3 Address Spaces Description
RAM: 256 Bytes
INPUT REGISTERS
LDRI
PROGRAM MEMORY
RAM
ST52X430 CORE
CONTROL UNIT
DPU
ALU
LDRC
is
I
I
I
I
Program memory will be described in further
details in the MEMORY section
2.3.1 RAM and STACK.
RAM memory consists of 256 general purpose 8-
bit RAM registers.
All the registers in RAM can be specified by using
a decimal address. For example, 0 identifies the
first register of RAM.
To read or write RAM registers LOAD instructions
must be used. See Table 2.5
Each interrupt level has its own set of flags, which
is saved in the STACK together with the Program
Counter. These flags are restored from the STACK
automatically when a RETI instruction is executed.
When the instructions like Interrupt request or
CALL are executed, a STACK level is used to push
the PC.
The STACK is located in RAM. For each level of
stack, 2 bytes of RAM are used. The values of this
stack are stored from the last RAM register
(address 255). The maximum level of stack
must be less than 128.
Input Registers: 20 8-bit registers
Output Registers 10 8-bit registers
Configuration Registers: 21 8-bit registers
Program memory up to 8K Bytes
LDCR
LDCE
LDPR
ON CHIP PERIPHERALS
PERIPHERAL REGISTERS
CONFIGURATION
REGISTERS
ST52T430/E430
PERIPHERAL
BLOCK
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