ST52T430K3M6 STMicroelectronics, ST52T430K3M6 Datasheet - Page 65

• Manufacturer Part Number: ST52T430K3M6
• Manufacturer: STMicroelectronics

Specifications of ST52T430K3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/UART
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5/5.8V
• Operating Supply Voltage (min): 2.7/3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 34
• Package Type: SSO
• Lead Free Status / Rohs Status: Not Compliant

Figure 11.3 SCI Status Input Register
After a RESET signal RST, the SCDR_TX block is
in IDLE state until it receives the enabling signal
TE=1, of Configuration Register 20.
Data is loaded on the peripheral register (OR 9) by
using the instruction LPPR or LDPE. If TE=1 the
data to be transmitted is transferred from DR_TX
block and flag of Input Register 19. TXEM is reset
to 0 in order to indicate that the SCDR_TX block is
full.
If the core supplies new data it can’t be loaded in
the SCDR_TX block until the current data hasn’t
been unloaded on the Shift Register block.
Therefore, data may be loaded in the SCDR_TX
Block only when TXEM is 1.
When the SHIFT REGISTER Block loads data to
be transmitted on an internal buffer, TXEND is
reset to 0 in order to indicate the beginning of a
new transmission. At the end of transmission
TXEND is set to 1, allowing to load new data
coming from SCDR_TX in the SHIFT REGISTER.
Note: TXEND = 1 does not mean SCDR_TX is
ready to receive new data. For this reason it is
better to utilize the TXEM signal in order to
synchronize the LDPR instruction to the SCI
TRANSMITTER block
If the ST52x430 core resets TE to 0, the
transmission is interrupted, but the SCI Transmitter
block completes the transmission in progress
before reset.
Warning: after the stop bit in SCI transmission an
idle time is present before the next start bit. This
time is equal to the duration of a bit transmission.
11.3 Baud Rate Generator Block
The Baud Rate Generator Block performs the
division of the clock master signal (CKM), in a set
D7 D6 D5 D4 D3 D2 D1 D0
Input Register 19
SCI_ST
of synchronism frequencies for the serial bit
reception/transmission on the external line.
Table 11.1 illustrates the set of frequencies
selected by means of BRSL (Configuration
Register 20).
Reception frequency (CLOCK_RX) is 16 times
higher than transmission frequency (CLOCK_TX).
The following example illustrates a simple way to
use SCI to receive and transmit data:
LDRC 1 155
LDCR 20 1
LDRC 1 252
LDCR 19 4
LDRC 1 170
LDPR 9 1
WAITI
LDRI 6 19
LDRI 1 18
TXEM
NOT USED
OVERR - OVERRUN ERROR
RXF
FRERR - FRAME ERROR
NSERR - NOISE ERROR
TXEND
R8
- TRANSMISSION DATA REGISTER EMPTY
- RECEIVE DATA REGISTER FULL
- END TRANSMISSION
- RECEIVED NINTH BIT
These instructions load value 155
on the Configuration Register 20
fixing the Baud Rate=9600, 8 bit
data, TE=1, RE=1; Parity; 1 stop bit.
SCI
frequency 20 MHz
Send data to transmission buffer
Save the SCI status register on the
RAM
Save the received data on a RAM
register
Interrupts
ST52T430/E430
enabled,
clock
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