ST52T430K3M6 STMicroelectronics, ST52T430K3M6 Datasheet - Page 46

• Manufacturer Part Number: ST52T430K3M6
• Manufacturer: STMicroelectronics

Specifications of ST52T430K3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/UART
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5/5.8V
• Operating Supply Voltage (min): 2.7/3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 34
• Package Type: SSO
• Lead Free Status / Rohs Status: Not Compliant

ST52T430/E430
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9 WATCHDOG TIMER
9.1 Operational Description
The Watchdog Timer (WDT) is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which cause the application program to
abandon its normal sequence. The WDT circuit
generates an MCU reset on expiry of a
programmed time period, unless the program
refreshes the WDT before the end of the
programmed time delay.
16 different delays can be selected by using the
WDT configuration register.
After the end of the delay programmed by the
configuration register if the WDT is activated (by
using the assembler instruction WDTSFR), it starts
a reset cycle pulling the reset pin low.
Once the WDT has been activated the application
program has to refresh this peripheral (by the
WDTSFR instruction) at regular intervals during
normal operation in order to prevent an MCU reset.
In order to stop the WDT during user program
execution the instruction WDTSLP has to be used.
Figure 9.1 Watchdog Block Diagram
WDTRFR
PRES CLK = CLK MASTER
RESET
WDTSLP
REG_CONF 2
PRESCALER
D3
D2
D1
The working frequency of the WDT (PRES CLK in
the Figure 9.1) is equal to the clock master. The
clock master is divided by 500, obtaining the WDT
CLK signal, which is used to fix the timeout of the
WDT.
Table 9.1 Watchdog Timing range (CLK=5
According to the WDT configuration register
values, a WDT delay may be defined between 0.1
ms and 937.5 mS when the clock master is 5 MHz.
By changing the clock master frequency the
timeout delay can be calculated according to the
configuration register values REG_CONF 2, as
described in the following section.
Warning: changing the REG_CONF2 value when
the WDT is active, a WDT reset is generated and
the CPU is restarted. To avoid this side effect, use
the WDTSLP instruction before changing the
REG_CONF2.
D0
max
min
WTD CLK
MHz)
GENERATOR
RESET
WDT timeout period (ms)
WDT
937.5
0.1
RESET