ST52T430K3M6 STMicroelectronics, ST52T430K3M6 Datasheet - Page 17

• Manufacturer Part Number: ST52T430K3M6
• Manufacturer: STMicroelectronics

Specifications of ST52T430K3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/UART
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5/5.8V
• Operating Supply Voltage (min): 2.7/3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 34
• Package Type: SSO
• Lead Free Status / Rohs Status: Not Compliant

Table 2.4 Output Registers
2.4 Arithmetic Logic Unit
The 8-bit Arithmetic Logic Unit (ALU) allows the
performance of arithmetic calculations and logic
instructions, which can be divided into 5 groups:
Load, Arithmetic, Jump, Interrupts and Program
Control instructions (refer to the ST52x430
Assembler Set for further details).
The
instruction consists of one clock pulse for each
Cycle plus 3 clock pulses for the decoding phase.
Table 2.5 Load instructions
Mnemonic
OR MNEMONIC NAME
computational
LDCE
LDCR
LDPR
LDRC
LDRE
LDRE
LDRR
LDFR
LDPE
LDPE
LDRI
PWM_0_RELOAD
PWM_1_RELOAD
PWM_ 2_ COUNT
PWM_2_RELOAD
PWM_0_COUNT
PWM_1_COUNT
SCI_TX_DATA
PORT_ A
PORT_ B
PORT_C
LDFR FUZZY_i_RAM RAM
time
LDRE RAMi, EPROMi
LDRE (RAMi), (RAMj)
LDCE conf, EPROM
LDRI RAM, inp_reg
LDPE per, EPROM
LDRR RAMi, RAMj
LDRC RAM, const
LDPE per, (RAM)
LDCR conf, RAM
LDPR reg, RAM
Instruction
required
TIMER/PWM 0 RELOAD REGISTER
TIMER/PWM 1 RELOAD REGISTER
TIMER/PWM 2 RELOAD REGISTER
TIMER/PWM 0 COUNTER
TIMER/PWM 1 COUNTER
TIMER/PWM 2 COUNTER
PERIPHERAL REGISTER
for
SCI DATA REGISTER
Load Instructions
each
PORT A OR
PORT B OR
PORT C OR
Bytes
The
multiplication
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values), see
Figure 2.5 and Figure 2.6.
WARNING: If the LSB of the multiplication
result is 0, the Zero flag is set although the
result is not 0.
3
3
3
3
3
3
3
3
3
3
3
ALU
of
Cycles
(MULT)
17
14
14
17
17
14
14
16
18
15
16
the
ST52x430
and
ADDRESS
Z
-
-
-
-
-
-
-
-
-
-
-
ST52T430/E430
0
1
2
3
4
5
6
7
8
9
division
can
S
-
-
-
-
-
-
-
-
-
-
-
perform
(DIV).
17/85
C
-
-
-
-
-
-
-
-
-
-
-