ST52T430K3M6 STMicroelectronics, ST52T430K3M6 Datasheet - Page 25

• Manufacturer Part Number: ST52T430K3M6
• Manufacturer: STMicroelectronics

Specifications of ST52T430K3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/UART
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5/5.8V
• Operating Supply Voltage (min): 2.7/3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 34
• Package Type: SSO
• Lead Free Status / Rohs Status: Not Compliant

4.2 Global Interrupt Request Enabling
When an Interrupt occurs, it generates a Global
Interrupt Pending (GIP), that can be masked by
software. After a GIP a Global Interrupt Request
(GIR) will be generated and Interrupt service
routine associated to the interrupt with higher
priority will start.
In order to avoid possible conflicts between
interrupt masking set in the main program, or
inside high level language compiler macros, the
GIP is hung up through the User Global Interrupt
Mask or the Macro Global Interrupt Mask (see
Figure 4.2).
UEGI/UDGI instruction switches on/off the User
Global Interrupt Mask, enabling/disabling the GIR
for the main program.
MEGI/MDGI instructions switch the Macro Global
Interrupt Mask on/off, in order to ensure that the
macro will not be broken.
4.3 Interrupt Sources
ST52x430 manages interrupt signals generated by
the internal peripherals (PWM/Timers, UART and
Analog to Digital Converter) or coming from the
INT/PC0 pin. The External Interrupt can be
programmed to be active on the rising or falling
edge of INT/PC0 signal by setting the PEXTINT bit
of the Configuration Register to 0.
WARNING: Changing the interrupt priority inside
an interrupt service routine can cause unwanted
interrupt requests.
Each peripheral can be programmed in order to
generate the associated interrupt; further details
are described in the related chapter.
4.4 Interrupt Maskability
The interrupts can be masked by configuring the
REG_CONF 0 by means of LDCR, or LDCE,
instruction. The interrupt is enabled when the bit
associated to the mask interrupt is “1". Viceversa,
when the bit is ”0", the interrupt is masked and is
kept pendent.
For example:
LDRC 10,6 //load the constant 6 in the
RAM Register 10
LDCR 0, 10 // set the CONF_REG 0 with
the value stored in the RAM Register
10
the result is CONF_REG0 =00000110 enabling the
interrupts deriving from the ADC (INT_ADC) and
from the PWM/TIMER 0 (INT_PWM/TIMER0).
Table 4.1 Configuration Register 0
Reset Configuration ‘000000’
Bit
0
1
2
3
4
5
6
7
PEXTINT
MSKTM0
MSKTM1
MSKTM2
Not used
MSKAD
Name
MSKE
MSCI
Description
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
External Interrupt
External Interrupt
External Interrupt
External Interrupt
ST52T430/E430
SCI Interrupt Not
Active on Falling
Active on Rising
PWM/TIMER 0
PWM/TIMER 1
PWM/TIMER 1
PWM/TIMER 2
PWM/TIMER 2
A/D Converter
A/D Converter
PWM/TIMER
SCI Interrupt
Description
Not Masked
Not Masked
Not Masked
Not Masked
Not Masked
0Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Masked
Masked
Masked
Masked
Masked
Masked
Masked
Polarity
Polarity
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