ST52T430K3M6 STMicroelectronics, ST52T430K3M6 Datasheet - Page 44

• Manufacturer Part Number: ST52T430K3M6
• Manufacturer: STMicroelectronics

Specifications of ST52T430K3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/UART
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5/5.8V
• Operating Supply Voltage (min): 2.7/3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 34
• Package Type: SSO
• Lead Free Status / Rohs Status: Not Compliant

ST52T430/E430
If input voltage is less than V
low) then the result is equal to 00h.
The A/D converter is linear and the digital result of
the conversion is provided by the following
formula:
Where Reference Voltage is V
The accuracy of the conversion is described in the
Electrical Characteristics Section.
The A/D converter is not affected by the WAIT
mode.
When the MCU enters HALT mode with A/D
converter enabled, the converter is disabled until
HALT mode is terminated and the start-up delay
has elapsed. A stabilization period is also required
before accurate conversions can be performed.
Figure 8.2 Conf. Register (REG_CONF 3)
44/85
Digitalresult
D 7
CH2 CH1 CH0 SCK SEQ POW LP STR
=
----------------------------------------------- -
referenceVoltage
255inputVoltage
REG_CONF 3
SS
dda
(voltage reference
- V
ss
.
8.2.1 Operating Modes.
Four main operating modes can be selected by
setting the values of the LP and SEQ bit in the A/D
configuration Register.
One Channel Single Mode
In this mode (SEQ = ‘0’’, LP = ‘0’) the A/D provides
an EOC signal after the end of channel i-th
conversion; then the A/D waits for a new start
event. Channel i-th is identified by the bit CH0,
CH1, CH2.
i.e CH(2:0) = ‘011’ means conversion of channel 3
then stop.
Multiple Channels Single Mode
In this mode (SEQ = ‘1’, LP = ‘0’) the A/D provides
an EOC signal after the end of the channels
sequence conversion identified by the bit CH0,
CH1, CH2; then the A/D waits for a new start event.
i.e. CH(2:0) = ‘011’ means conversion of channels
0,1,2 and 3 then stop.
D0
START/STOP
CONVERSION MODE SEL.
ON/OFF A/D
CONVERSION MODE SEL.
CLOCK SELECTOR
CHANNELS SEL.