ST52T430K3M6 STMicroelectronics, ST52T430K3M6 Datasheet - Page 45

• Manufacturer Part Number: ST52T430K3M6
• Manufacturer: STMicroelectronics

Specifications of ST52T430K3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/UART
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5/5.8V
• Operating Supply Voltage (min): 2.7/3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 34
• Package Type: SSO
• Lead Free Status / Rohs Status: Not Compliant

One Channel Continuous Mode
In this mode (SEQ = ‘0’’, LP = ‘1’) a continuous
conversion flow is entered by a starting event on
the channel selected by the CH0, CH1, CH2 bits
For example: CH(2:0) = ‘011’ means continuous
conversion of channel 3. At the end of each
conversion the relative IR is updated with the last
conversion result, while the former value is lost.
To stop the conversion STR has to be set to ‘0’.
Multiple Channels Continuous Mode
In this mode (SEQ = ‘1’’, LP = ‘1’) a continuous
conversion flow is entered by a starting event on
the channels selected by the CH0, CH1, CH2 bits.
i.e CH(2:0) = ‘011’ means continuous conversion
of channel 0,1,2 and 3.
At the end of each conversion the relative IRs are
updated with the last conversion results, while the
former values are lost.
To stop the conversion STR has to be set to ‘0’.
8.2.2 Power Down Mode.
Before enabling any A/D operation mode, set the
POW bit of the A/D configuration register to ‘1’ at
least 60
enable the biasing circuit inside the analog section
of the converter. Clearing the POW bit (POW = ‘0’)
is useful when the A/D is not used, reducing the
total chip power consumption. This state is also the
reset configuration and it is forced by hardware
when the core is in HALT state (after a HALT
instruction execution).
8.3 A/D Registers Description
The result of the conversions of the 8 available
channels are loaded in the 8 Input Register from
decimal address 1 to decimal address 8. (IR (1:8)
see Table 2.2)). Every IR(1:8) is reloaded with a
new value at the end of the conversion of the
correspondent analog input.
By using the assembler instruction:
LDRI RAM_Reg. IR_i
the value stored in the i-th IR is transferred on the
RAM location RAM_Reg.
The A/D configuration register is the REG_CONF
3. Figure 6.2 illustrates the structure of this
register, which manages the A/D logic operation.
The A/D configuration register (REG_CONF 3) is
programmable as following:
b7-b5 = CH2, CH1, CH0: Last Conversion
Address. These 3 bits define the last analog input.
The first analog input is converted, then the
address is incremented for the successive
conversion until the channel identified by CH0-
CH2 is converted. The (CH2, CH1, CH0) bits
define the group of channels to be scanned. When
s before the first conversion starts to
setting CH2=0 CH1=0 CH0=0 only channel 0 is
converted.
b4 = SCK: Master clock divider. ST52x430 can
work with a clock frequency up to 20 MHz. The
SCK must be set to ‘1’ when the ST52x430 clock is
higher then 10 MHz. It is useful to set SCK = ‘1’
even when the clock master is lower than 10 MHz
and a high accuracy is required.
b3 = SEQ: Multiple/Single channel. When SEQ is
set to ‘0’ the channel identified by CH(2:0) is
converted. If SEQ is set to ‘1’ the group of channels
identified by CH(2:0) are converted.
b2= POW: Power Up/ Power Down. A logical ‘1’
enables the A/D logic and analog circuitry.
Logical level ‘0’ disables all power consuming
logic, allowing a low power idle status.
b1 = LP: Continuous/Single. When this bit is set to
‘1’ (continuous mode), the first conversion
sequences are started by the STR bit then a
continuous conversion flow is processed.
When LP=’0’ (single mode) only one sequence of
conversions is started when STR is set.
b0 = STR: Start/Stop. A logical level ‘1’ enables
starting a conversion sequence; a logical level ‘0’
stops the conversion. When the A/D is running in
the Single Modes (LP=’0’), this bit is hardware
reset at the end of a conversion sequence.
Table 8.1 A/D Conf. Register (Reg_Conf 3)
Bit
0
1
2
3
4
5
6
7
CH(2:0)
Name
POW
SEQ
STR
SCK
LP
Value
000
001
010
100
101
011
110
111
0
1
0
1
0
1
0
1
0
1
Multiple Channels Conv
Single Channel Conv.
Single Conversion
Clock not Divided
Start Conversion
Stop Conversion
Clock Divided
ST52T430/E430
Description
Continuous
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
A/D OFF
A/D ON
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