ST52T430K3M6 STMicroelectronics, ST52T430K3M6 Datasheet - Page 27

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ST52T430K3M6

Manufacturer Part Number
ST52T430K3M6
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST52T430K3M6

Cpu Family
ST52
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SCI/UART
Program Memory Type
EPROM
Program Memory Size
8KB
Total Internal Ram Size
256Byte
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5/5.8V
Operating Supply Voltage (min)
2.7/3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
34
Package Type
SSO
Lead Free Status / Rohs Status
Not Compliant

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Figure 4.5 Interrupt Configuration Register 17 & 18
4.5 Interrupt Priority
Seven priority levels are available: level 6 has the
lowest priority, level 0 has the highest priority.
Level 6 is associated to the Main Program, levels 5
to 1 are programmable by means of the priority
registers
REG_CONF18 (see Figure 4.5 and Table 4.3);
whereas the higher level is related to the external
interrupt (INT_EXT).
PWM/Timers, UART and ADC are identified by a
three-bit Peripheral Codes (see Table 4.2); in order
to set the i-th priority level the user must write the
peripheral label i in the related INTi priority level.
i.e.
LDRC
193=’11000001’ in the RAM Register 10)
LDRC
168=’10101000’ in the RAM Register 11)
LDCR 17, 10 // set the REG_CONF17=
‘11000001’
LDCR 18, 11 // set the REG_CONF18=
‘10101000’
The following priority levels are defined:
I
I
Level 1: INT_PWM/TIMER0 (PWM/TIMER 0
Code: 001)
Level 2: INT_ADC (ADC Code: 000)
D15
10,
11,
D14
D13
called
193
168
REG_CONF18
D12
//(load
//(load
D11
REG_CONF17
D10
D9
the
the
Interrupts Priority
D8
value
value
and
D7
D6
Table 4.3 Conf. Register 17 & 18 Description
I
I
I
9,10,11
12,13,1
Level 3: Int_PWM/Timer2 (PWM/TIMER 2
Code: 011)
Level 4: INT_UART (UART Code: 100)
Level 5: INT_PWM/TIMER1 (PWM/TIMER 1
Code: 010)
D5
0, 1,2
3, 4,5
6,7,8
Bit
4
REG_CONF17
D4
Name
D3
INT1
INT2
INT3
INT4
INT5
D2
Periphera
Periphera
Periphera
Periphera
Periphera
l Code
l Code
l Code
l Code
l Code
D1
Value
D0
ST52T430/E430
Medium-High
Medium-Low
INT 1
INT 2
INT 3
INT 4
INT 5
Not Used
Very Low
Level
High
Low
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