ST52T430K3M6 STMicroelectronics, ST52T430K3M6 Datasheet - Page 42

• Manufacturer Part Number: ST52T430K3M6
• Manufacturer: STMicroelectronics

Specifications of ST52T430K3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/UART
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5/5.8V
• Operating Supply Voltage (min): 2.7/3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 34
• Package Type: SSO
• Lead Free Status / Rohs Status: Not Compliant

ST52T430/E430
Example 1:
IF Input
is codified by the following instructions:
Example 2, the priority of the operator is fixed by the brackets:
IF (Input
At the end of the fuzzy rule, by using the instruction OUT RAM_reg, a byte is written. Afterwards, the
control of the algorithm returns to the CU.
42/85
LDN 1 1
LDP 4 12
FZAND
LDK
LDP 3 8
FZOR
CON crisp
LDP 3 1
LDN 4 15
FZAND
SKM
LDN 2 14
FZOR
LDK
LDM
FZOR
CON crisp
LDP 1 6
1
3
IS NOT Mbf
IS Mbf
1
2
calculates the NOT
fixes the
implements the operation AND between the results obtained with the previous instructions
stores the result of the previous operation in internal DPU registers
fixes the
implements the operation OR between the results obtained with the previous instructions
multiplies the result of the last
fixes the
calculates the NOT
implements the operation AND between the results obtained with the previous instructions
stores the result of the previous operation in register M
fixes the
calculates the NOT
implements the operation OR between the results obtained with the previous instructions
stores the result of the previous operation in internal DPU registers
copies the value of the register M in internal DPU registers
multiplies the result of the last
implements the operation OR between the last two values stored in DPU registers
1
AND Input
1
AND Input
value of Input
value of Input
value of Input
value of Input
4
IS NOT Mbf
4
is Mbf
value of Input
value of Input
value of Input
4
3
3
1
12
with Mbf
with Mbf
with Mbf
with Mbf
15
OR Input
) OR (Input
operation with the crisp value crisp
operation with the crisp value crisp
12
8
1
6
1
4
6
and stores the result in internal registers
and stores the result in internal registers
and stores the result in internal registers
with Mbf
with Mbf
with Mbf
and stores the result in internal registers
3
IS Mbf
1
IS Mbf
15
14
1
8
and stores the result in internal registers
and stores the result in internal registers
and stores the result in internal registers
THEN Crisp
6
OR Input
6
1
IS NOT Mbf
1
2
14
) THEN Crisp
2