ST52T430K3M6 STMicroelectronics, ST52T430K3M6 Datasheet - Page 64

• Manufacturer Part Number: ST52T430K3M6
• Manufacturer: STMicroelectronics

Specifications of ST52T430K3M6

• Cpu Family: ST52
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/UART
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5/5.8V
• Operating Supply Voltage (min): 2.7/3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 34
• Package Type: SSO
• Lead Free Status / Rohs Status: Not Compliant

ST52T430/E430
A frame error can occur if the parity check hasn’t
been successfully achieved or if the STOP bit
hasn’t been detected.
If the Recovery Buffer Block receives 10
consecutive bits at logic level 0, a break error
occurs and an interrupt routine request starts.
SCDR_RX Block
It is a finite state machine synchronized with the
clock master signal, CKM.
The SCDR_RX block waits for the signal of
complete reception from the Recovery Buffer, in
order to load the word received. Moreover, the
SCDR_RX block loads the values of FRERR and
NSERR flag bits (Input Register 19), and sets the
RXF flag to 1.
Data is transferred to RAM and the RXF flag is
reset to 0 by using the LDRI instruction in order to
indicate that the SCDR_RX block is empty.
If new data arrives before the previous one has
been transferred to Register File, an overrun error
occurs and OVERR flag of Input Register 19 is set
to 1.
Warning: The SCI looses synchronization in data
reception
consecutively, without an idle time of at least 3/16
of bit time (3 SCI CLOCK_RX cycles).
To avoid lost of synchronization when two
consecutive bytes are received by the ST52x430
SCI peripheral, the external Transmitter device
must guarantee an idle time corresponding to 3
CLOCK_RX cycles between the stop bit of each
byte and the start bit of the successive byte.
As an implementation suggestion, this can be
achieved by configuring the external Transmitter
device with 2 Stop bits and the ST52x430 SCI
configured as a Receiver with 1 Stop bit.
11.2 SCI Transmitter Block
The SCI Transmitter Block consists of the following
blocks:
synchronized, respectively, with the clock master
signal (CKM) and the CLOCK_TX.
The whole block receives the settings for the
following transmission modes (see Table 11.1)
through Configuration Register 20 (M bits):
I
I
I
I
In case of 9 bit frame transmission, the most
significative bit arrives through T8 of the
Configuration Register 20.
64/85
8-bit word and a single stop signal
8-bit word plus a parity bit and a single stop
signal
8-bit word plus a double stop signal
9-bit word
SCDR_TX
when
two
and
bytes
SHIFT
are
REGISTER,
received
Instead, in an 8-bit transmission T8 is used to
configure SCI according to information contained
in M (see Table 11.1). In particular, it is used to
choose the polarity control (even or odds) in order
to implement the parity check.
Table 11.2 Configuration Register 19 Setting
Bit
0
1
2
3
4
5
6
7
Name
TDRE
RDRF
ECKF
OVR
BRK
TXC
Value
00
01
10
11
0
1
0
1
0
1
0
1
0
1
-
Register Full Interrupt
Register Full Interrupt
Data Register Empty
Data Register Empty
SCI Received Data
SCI Received Data
SCI Overrun Error
SCI Overrun Error
Interrupt Disabled
SCI Transmission
Interrupt Disabled
SCI Transmission
Interrupt Disabled
Interrupt Disabled
Interrupt Enabled
Interrupt Enabled
Interrupt Enabled
Interrupt Enabled
SCI Break Error
SCI Break Error
Transmission
Transmission
Description
Not used
Disabled
SCI End
SCI End
Enabled
10 MHz
20 MHz
5 MHz
5 MHz