A25L040O-F AMIC, A25L040O-F Datasheet - Page 19

• Manufacturer Part Number: A25L040O-F
• Description: 58T1309
• Manufacturer: AMIC

Specifications of A25L040O-F

• Memory Type: Flash
• Memory Size: 4Mbit
• Memory Configuration: 4M X 1
• Interface Type: Serial, SPI
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes

Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits
inside the chosen sector. Before it can be accepted, a Write
Enable (WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip
Select (
Data Input (DIO). Chip Select (
entire duration of the sequence.
The instruction sequence is shown in Figure 13. Chip Select
(
code has been latched in, otherwise the Sector Erase
Figure 13. Sector Erase (SE) Instruction Sequence
(October, 2010, Version 1.2)
S
) must be driven High after the eighth bit of the instruction
S
) Low, followed by the instruction code on Serial
DIO
C
S
Note: Address bits A23 to A19 are Don’t Care, for A25L040.
S
0 1
) must be driven Low for the
2 3 4
Instruction
5 6
7
MSB
23
23
8
18
22 21
instruction is not executed. As soon as Chip Select (
driven High, the self-timed Sector Erase cycle (whose
duration is t
progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is
0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is
protected by the Block Protect (BP2, BP1, BP0) bits (see
table 1. and table 2.) is not executed.
9
24-Bit Address
10
3 2 1
28 29 30 31
SE
) is initiated. While the Sector Erase cycle is in
0 0
AMIC Technology Corp.
A25L040 Series
S
) is