A25L040O-F AMIC, A25L040O-F Datasheet - Page 21

• Manufacturer Part Number: A25L040O-F
• Description: 58T1309
• Manufacturer: AMIC

Specifications of A25L040O-F

• Memory Type: Flash
• Memory Size: 4Mbit
• Memory Configuration: 4M X 1
• Interface Type: Serial, SPI
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes

Chip Erase (CE)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before
it can be accepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip
Select (
Data Input (DIO). Chip Select (
entire duration of the sequence.
The instruction sequence is shown in Figure 15. Chip Select
(
code has been latched in, otherwise the Bulk Erase instruction
Figure 15. Chip Erase (CE) Instruction Sequence
(October, 2010, Version 1.2)
S
) must be driven High after the eighth bit of the instruction
S
) Low, followed by the instruction code on Serial
DIO
C
S
S
) must be driven Low for the
Note: Address bits A23 to A19 are Don’t Care, for A25L040.
0
1 2 3
Instruction
20
4 5 6 7
is not executed. As soon as Chip Select (
the self-timed Chip Erase cycle (whose duration is t
initiated. While the Chip Erase cycle is in progress, the Status
Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during
the self-timed Chip Erase cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the
Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block
Protect (BP2, BP1, BP0) bits are 0. The Chip Erase (CE)
instruction is ignored if one, or more, blocks are protected.
AMIC Technology Corp.
A25L040 Series
S
) is driven High,
CE
) is