A25L040O-F AMIC, A25L040O-F Datasheet - Page 7

• Manufacturer Part Number: A25L040O-F
• Description: 58T1309
• Manufacturer: AMIC

Specifications of A25L040O-F

• Memory Type: Flash
• Memory Size: 4Mbit
• Memory Configuration: 4M X 1
• Interface Type: Serial, SPI
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes

Hold Condition
The Hold (
communications with the device without resetting the clocking
sequence. However, taking this signal Low does not
terminate any Write Status Register, Program or Erase cycle
that is currently in progress.
To enter the Hold condition, the device must be selected, with
Chip Select (
The Hold condition starts on the falling edge of the Hold
(
(C) being Low (as shown in Figure 3.).
The Hold condition ends on the rising edge of the Hold
(
(C) being Low.
If the falling edge does not coincide with Serial Clock (C)
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after
Figure 3. Hold Condition Activation
(October, 2010, Version 1.2)
Note: 1. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
Table 1. Protected Area Sizes
A25L040
HOLD
HOLD
BP2 Bit
0
0
0
0
1
1
1
1
Status Register Content
) signal, provided that this coincides with Serial Clock
) signal, provided that this coincides with Serial Clock
HOLD
S
) Low.
BP1 Bit
0
0
1
1
0
0
1
1
) signal is used to pause any serial
HOLD
C
BP0 Bit
0
1
0
1
0
1
0
1
none
Upper eighth (block: 7)
Upper quarter (two blocks: 6 to 7)
Upper half (four blocks: 4 to 7)
All blocks (eight blocks: 0 to 7)
All blocks (eight blocks: 0 to 7)
All blocks (eight blocks: 0 to 7)
All blocks (eight blocks: 0 to 7)
(standard use)
Protected Area
Condition
Hold
6
Serial Clock (C) next goes Low. This is shown in Figure 3.
During the Hold condition, the Serial Data Output (DO) is high
impedance, and Serial Data Input (DIO) and Serial Clock (C)
are Don’t Care.
Normally, the device is kept selected, with Chip Select (
driven Low, for the whole duration of the Hold condition. This
is to ensure that the state of the internal logic remains
unchanged from the moment of entering the Hold condition.
If Chip Select (
condition, this has the effect of resetting the internal logic of
the device. To restart communication with the device, it is
necessary to drive Hold (
Chip Select (
back to the Hold condition.
(non-standard use)
Memory Content
Condition
S
Hold
All blocks
Lower seven-eighths (7 blocks: 0 to 6)
Lower three-quarters (6 blocks: 0 to 5)
Lower half (4 blocks: 0 to 3)
None
None
None
None
S
) Low. This prevents the device from going
) goes High while the device is in the Hold
1
AMIC Technology Corp.
HOLD
Unprotected Area
) High, and then to drive
A25L040 Series
S
)