A25L040O-F AMIC, A25L040O-F Datasheet - Page 9

• Manufacturer Part Number: A25L040O-F
• Description: 58T1309
• Manufacturer: AMIC

Specifications of A25L040O-F

• Memory Type: Flash
• Memory Size: 4Mbit
• Memory Configuration: 4M X 1
• Interface Type: Serial, SPI
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes

INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input (DIO) is sampled on the first rising edge of
Serial Clock (C) after Chip Select (
one-byte instruction code must be shifted in to the device,
most significant bit first, on Serial Data Input (DIO), each bit
being latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Status Register (RDSR) or
Release from Deep Power-down, Read Device Identification
and Read Electronic Signature (RES) instruction, the shifted-in
instruction sequence is followed by a data-out sequence. Chip
Select (
Table 3. Instruction Set
Note: (1) DIO = (D
(October, 2010, Version 1.2)
WREN
WRDI
RDSR
WRSR
READ
FAST_READ
FAST_READ_DUAL
_OUTPUT
FAST_READ_DUAL
_INPUT-OUTPUT
PP
SE
BE
CE
DP
RDID
REMS
RES
(3) ADD= (00h) will output manufacturer’s ID first and ADD = (01h) will output device ID first
(2) Dual Input, DIO = (A22, A20, A18, ………, A6, A4, A2, A0)
Instruction
S
DO = (D
) can be driven High after any bit of the data-out
7
6
, D
, D
DO = (A23, A21, A19, …….., A7, A5, A3, A1)
5
4
, D
, D
Write Enable
Read Data Bytes
Page Program
Write Disable
Read Status Register
Write Status Register
Read Data Bytes at Higher Speed
Read Data Bytes at Higher Speed by
Dual Output
Read Data Bytes at Higher Speed by
Dual Input and Dual Output
Sector Erase
Block Erase
Chip Erase
Deep Power-down
Read Device Identification
Read Electronic Manufacturer & Device
Identification
Release from Deep Power-down, and
Read Electronic Signature
Release from Deep Power-down
3
2
, D
, D
1
0
)
)
S
) is driven Low. Then, the
(1)
Description
(1)
8
sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Block
Erase (BE), Chip Erase (CE), Write Status Register (WRSR),
Write Enable (WREN), Write Disable (WRDI) or Deep
Power-down (DP) instruction, Chip Select (
High exactly at a byte boundary, otherwise the instruction is
rejected, and is not executed. That is, Chip Select (
driven High when the number of clock pulses after Chip Select
(
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
S
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
0010 0000
1101 1000
1100 0111
1011 1001
1001 1111
1001 0000
1010 1011
00111011
10111011
) being driven Low is an exact multiple of eight.
Instruction Code
One-byte
0Bh
BBh
D8h
C7h
B9h
ABh
06h
04h
05h
01h
03h
3Bh
02h
20h
9Fh
90h
AMIC Technology Corp.
Address
Bytes
3
1
0
0
0
0
3
3
3
3
3
3
0
0
0
0
0
(2)
(3)
A25L040 Series
Dummy
Bytes
1
0
0
0
0
0
1
1
0
0
0
0
0
0
2
3
0
S
(2)
) must be driven
1 to 256
Bytes
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to ∞
S
Data
) must
0
0
1
0
0
0
0
0