A25L040O-F AMIC, A25L040O-F Datasheet - Page 20

• Manufacturer Part Number: A25L040O-F
• Description: 58T1309
• Manufacturer: AMIC

Specifications of A25L040O-F

• Memory Type: Flash
• Memory Size: 4Mbit
• Memory Configuration: 4M X 1
• Interface Type: Serial, SPI
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes

Block Erase (BE)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside
the chosen block. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL).
The Block Erase (BE) instruction is entered by driving Chip
Select (
Data Input (DIO). Chip Select (
entire duration of the sequence.
The instruction sequence is shown in Figure 14. Chip Select
(
code has been latched in, otherwise the Block Erase
Figure 14. Block Erase (BE) Instruction Sequence
(October, 2010, Version 1.2)
S
) must be driven High after the eighth bit of the instruction
S
) Low, followed by the instruction code on Serial
DIO
C
S
Note: Address bits A23 to A19 are Don’t Care, for A25L040.
S
) must be driven Low for the
0 1
2 3 4
Instruction
5 6
7
MSB
19
23
23
8
instruction is not executed. As soon as Chip Select (
driven High, the self-timed Block Erase cycle (whose duration
is t
the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit
is 1 during the self-timed Block Erase cycle, and is 0 when it
is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a page which is
protected by the Block Protect (BP2, BP1, BP0) bits (see
table 1. and table 2.) is not executed.
22 21
BE
9
24-Bit Address
) is initiated. While the Block Erase cycle is in progress,
10
3 2 1 0 0
28 29 30 31
AMIC Technology Corp.
A25L040 Series
S
) is