MT29F8G08AAAWP-ET:ATR Micron Technology Inc, MT29F8G08AAAWP-ET:ATR Datasheet - Page 9

• Manufacturer Part Number: MT29F8G08AAAWP-ET:ATR
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08AAAWP-ET:ATR

• Cell Type: NAND
• Density: 8Gb
• Access Time (max): 18ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Table 1:
PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
2gb_nand_m29b__2.fm - Rev. I 1/06 EN
(3V device only)
MT29FxG08
MT29FxG16
R/B#, R/B2#
CE#, CE2#
I/O[15:0]
Symbol
I/O[7:0]
PRE
DNU
WE#
WP#
ALE
CLE
RE#
V
V
NC
CC
SS
1
Pin Descriptions
Notes: 1. The PRE function is not supported on extended-temperature devices.
Output
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Type
I/O
–
–
Address latch enable: During the time ALE is HIGH, address information is
transferred from I/O[7:0] into the on-chip address register upon a LOW-to-HIGH
transition on WE#
should be driven LOW.
Chip enable: Gates transfers between the host system and the NAND device. Once
the device starts a PROGRAM or ERASE operation, the chip enable pin can be de-
asserted. For the 8Gb configuration, CE# controls the first 4Gb of memory; CE2#
controls the second 4Gb. See the Bus Operation section, starting on “Bus
Operation” on page 16 for additional operational details.
Command latch enable: When CLE is HIGH, information is transferred from
I/O[7:0] to the on-chip command register on the rising edge of WE#. When
command information is not being loaded, the CLE pin should be driven LOW.
Power-on read enable: Enables the auto-read function when at Vcc. See “Bus
Operation” on page 16, for additional details.
Read enable: Gates transfers from the NAND device to the host system.
Write enable: Gates transfers from the host system to the NAND device.
Write protect: Pin protects against inadvertent PROGRAM and ERASE operations.
All PROGRAM and ERASE operations are disabled when the WP# pin is LOW.
Data inputs/outputs: The bidirectional I/O pins transfer address, data, and
instruction information. Data is output only during READ operations; at other
times the I/O pins are inputs.
Ready/busy: An open-drain, active-LOW output, that uses an external pull-up
resistor. The pin is used to indicate when the chip is processing a PROGRAM or
ERASE operation. The pin is also used during a READ operation to indicate when
data is being transferred from the array into the serial data register. Once these
operations have completed, the R/B# returns to the High-Z state. In the 8Gb
configuration, R/B# is for the 4Gb of memory enabled by CE#; R/B2# is for the 4Gb
of memory enabled by CE2#.
V
V
Do not use: Must be left floating.
No connect: NC pins are not internally connected. These pins can be driven or left
unconnected.
CC
SS
: The V
: The V
SS
CC
2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
pin is the ground connection.
pin is the power supply pin.
.
When address information is not being loaded, the ALE pin
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
General Description
©2004 Micron Technology, Inc. All rights reserved.