cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 134

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

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19.3
Software interacts with the UART by accessing the UART
registers. There are eight registers, as listed in Table 60.
19.3.1
The URBUF register is a byte-wide, read/write register used
to receive each data byte.
19.3.2
The UTBUF register is a byte-wide, read/write register used
to transmit each data byte.
7
7
UMDSL1
UMDSL2
UICTRL
USPOS
URBUF
UBAUD
UTBUF
USTAT
UOVR
Name
UPSR
UFRS
UART Receive Data Buffer (URBUF)
UART REGISTERS
UART Transmit Data Buffer (UTBUF)
Table 60 UART Registers
FF FE4Ch
FF FE4Eh
FF FE4Ah
FF FE42h
FF FE40h
FF FE48h
FF FE46h
FF FE44h
FF FE50h
FF FE52h
FF FE54h
Address
URBUF
UTBUF
UART Interrupt Control
UART Status Register
UART Transmit Data
UART Receive Data
UART Frame Select
UART Mode Select
UART Mode Select
UART Oversample
UART Baud Rate
UART Baud Rate
Position Register
UART Sample
Rate Register
Description
Register 1
Register 2
Prescaler
Register
Register
Divisor
Buffer
Buffer
0
0
134
19.3.3
The UPSR register is a byte-wide, read/write register that
contains the 5-bit clock prescaler and the upper three bits of
the baud rate divisor. This register is cleared upon reset.
The register format is shown below.
UPSC
UDIV10:8
19.3.4
The UBAUD register is a byte-wide, read/write register that
contains the lower eight bits of the baud rate divisor. The
register contents are unknown at power-up and are left un-
changed by a reset operation. The register format is shown
below.
UDIV7:0
19.3.5
The UFRS register is a byte-wide, read/write register that
controls the frame format, including the number of data bits,
number of stop bits, and parity type. This register is cleared
upon reset. The register format is shown below.
UCHAR
Reserved UPEN
7
7
7
UART Baud Rate Prescaler (UPSR)
UART Baud Rate Divisor (UBAUD)
UART Frame Select Register (UFRS)
The Prescaler field specifies the prescaler val-
ue used for dividing the System Clock in the
first stage of the two-stage divider chain. For
the prescaler factors corresponding to each 5-
bit value, see Table 59.
The Baud Rate Divisor field holds the three
most significant bits (bits 10, 9, and 8) of the
UART baud rate divisor used in the second
stage of the two-stage divider chain. The re-
maining bits of the baud rate divisor are held
in the UBAUD register.
The Baud Rate Divisor field holds the eight
lowest-order bits of the UART baud rate divi-
sor used in the second stage of the two-stage
divider chain. The three most significant bits
are held in the UPSR register. The divisor val-
ue used is (UDIV[10:0] + 1).
The Character Frame Format field selects the
number of data bits per frame, not including
the parity bit, as follows:
00 – 8 data bits per frame.
01 – 7 data bits per frame.
10 – 9 data bits per frame.
11 – Loop-back mode, 9 data bits per frame.
6
UPSC
UPSEL
5
UDIV7:0
4
UXB9
3
3
2
USTP
UDIV10:8
2
UCHAR
1
0
0
0