cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 3

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

2.0
CPU Features
T Fully static RISC processor core, capable of operating
T Minimum 41.7 ns instruction cycle time with a 24-MHz in-
T 30 independently vectored peripheral interrupts
On-Chip Memory
T 256K bytes reprogrammable Flash program memory
T 8K bytes Flash data memory
T 10K bytes of static RAM data memory
T Addresses up to 8 Mbytes of external memory
Broad Range of Hardware Communications Peripherals
T Bluetooth Lower Link Controller (LLC) including a shared
T Full CAN interface with 15 message buffers conforming
T ACCESS.bus serial bus (compatible with Philips I
T 8/16-bit SPI, Microwire/Plus serial interface
T Universal Asynchronous Receiver/Transmitter (UART)
T Advanced Audio Interface (AAI) to connect to external 8/
T CVSD/PCM converter supporting one bidirectional audio
General-Purpose Hardware Peripherals
T Dual 16-bit Multi-Function Timer
T Versatile Timer Unit with four subsystems (VTU)
T Four channel DMA controller
T Timing and Watchdog Unit
Flexible I/O
T Up to 40 general-purpose I/O pins (shared with on-chip
CP3BT13 Connectivity Processor Selection Guide
from 0 to 24 MHz with zero wait/hold states
ternal clock frequency, based on a 12-MHz external input
4.5K byte Bluetooth RAM and 1K byte Bluetooth Se-
quencer RAM
to CAN specification 2.0B active
13-bit PCM Codecs as well as to ISDN-Controllers
through the IOM-2 interface (slave only)
connection
peripheral I/O pins)
CP3BT13G38
CP3BT13K38
NSID
Features
Speed
(MHz)
24
24
Temp. Range
-40° to +85°C
-40° to +85°C
Program
(kBytes)
2
Flash
C bus)
256
256
3
T Programmable I/O pin characteristics: TRI-STATE out-
T Schmitt triggers on general purpose inputs
T Multi-Input Wakeup
Extensive Power and Clock Management Support
T On-chip Phase Locked Loop
T Support for multiple clock options
T Dual clock and reset
T Power-down modes
Power Supply
T I/O port operation at 2.5V to 3.3V
T Core logic operation at 2.5V
T On-chip power-on reset
Temperature Range
T -40°C to +85°C (Industrial)
Packages
T CSP-48, LQFP-100
Complete Development Environment
T Pre-integrated hardware and software support for rapid
T Integrated environment
T Project manager
T Multi-file C source editor
T High-level C source debugger
T Comprehensive, integrated, one-stop technical support
Bluetooth Protocol Stack
T Applications can interface to the high-level protocols or
T Transport layer support allows HCI command-based in-
T Baseband (Link Controller) minimizes the performance
(kBytes)
put, push-pull output, weak pull-up input, high-imped-
ance input
prototyping and production
directly to the low-level Host Controller Interface (HCI)
terface over UART port
demand on the CPU
Flash
Data
8
8
(kBytes)
SRAM
10
10
External
Address
Lines
23
0
I/Os
40
23
www.national.com
LQFP-100
Package
CSP-48
Type