cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 36

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

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WRPROT
8.5
There is a separate interface for the program flash and data
flash memories. The same set of registers exist in both in-
terfaces. In most cases they are independent of each other,
but in some cases the program flash interface controls the
interface for both memories, as indicated in the following
sections. Table 18 lists the registers.
FMMERASE0
FMPERASE
FF F94Ch
FMSTART
FF F94Eh
FMPROG
FF F95Ah
FF F940h
FF F942h
FM0WER
FF F944h
FM1WER
FF F946h
FF F950h
FF F952h
FF F954h
FF F956h
FF F958h
FMTRAN
Program
FMCTRL
Memory
FMIBAR
FMIBDR
FMSTAT
FMPSR
Table 18 Flash Memory Interface Registers
FLASH MEMORY INTERFACE
REGISTERS
The WRPROT field controls the global write
protection mechanism for the on-chip flash
program memory. If a majority of the three
WRPROT bits are clear, the flash program
memory is protected against write access
from any source and read access from the se-
rial debug interface. If a majority of the WR-
PROT bits are set, write access is allowed.
FSMMERASE0
FSMPERASE
FSMSTART
FSM0WER
FSMPROG
FSMTRAN
FSMCTRL
FSMIBDR
FF F74Ch
FSMIBAR
FSMSTAT
FF F74Eh
FF F75Ah
FF F740h
FF F742h
FF F744h
FF F750h
FF F752h
FF F754h
FF F756h
FF F758h
FSMPSR
Memory
Data
N/A
Flash Memory Module
Write Enable Register
Write Enable Register
Time Reload Register
Flash Memory Page
Flash Memory Start
Programming Time
Erase Time Reload
Erase Time Reload
Prescaler Register
Information Block
Information Block
Address Register
Address Register
Flash Memory 0
Flash Memory 1
Control Register
Reload Register
Reload Register
Status Register
Transition Time
Flash Memory
Flash Memory
Flash Memory
Flash Memory
Flash Memory
Flash Memory
Flash Memory
Description
Register 0
Register
36
8.5.1
The FMIBAR register specifies the 8-bit address for read or
write access to an information block. Because only word ac-
cess to the information blocks is supported, the least signif-
icant bit (LSB) of the FMIBAR must be 0 (word-aligned). The
hardware automatically clears the LSB, without regard to
the value written to the bit. The FMIBAR register is cleared
after device reset. The CPU bus master has read/write ac-
cess to this register.
IBA
8.5.2
The FMIBDR register holds the 16-bit data for read or write
access to an information block. The FMIBDR register is
cleared after device reset. The CPU bus master has read/
write access to this register.
IBD
15
15
FF F95Eh
FMMEND
FF F960h
FF F962h
FF F964h
FF F966h
FF F968h
Program
Memory
FMEND
FMRCV
FMAR0
FMAR1
FMAR2
Table 18 Flash Memory Interface Registers
Flash Memory Information Block Address
Register (FMIBAR/FSMIBAR)
Flash Memory Information Block Data Register
(FMIBDR/FSMIBDR)
Reserved
The Information Block Address field holds the
word-aligned address of an information block
location accessed during a read or write
transaction. The LSB of the IBA field is always
clear.
The Information Block Data field holds the
data word for access to an information block.
For write operations the IBD field holds the
data word to be programmed into the informa-
tion block location specified by the IBA ad-
FSMMEND
FF F75Eh
FF F760h
FF F762h
FF F764h
FF F766h
FF F768h
FSMEND
FSMRCV
FSMAR0
FSMAR1
FSMAR2
Memory
Data
8
IBD
7
Flash Memory Module
Time Reload Register
Auto-Read Register 0
Auto-Read Register 1
Auto-Read Register 2
Flash Memory End
Erase End Time
Reload Register
Reload Register
Recovery Time
Flash Memory
Flash Memory
Flash Memory
Flash Memory
Description
IBA
0
0