cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 49

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

10.3.2
The EXNMI register is a byte-wide read/write register. It in-
dicates the current value of the NMI pin and controls the
NMI interrupt trap generation based on a falling edge of the
NMI pin. TST, EN and ENLCK are cleared on reset. When
writing to this register, all reserved bits must be written with
0 for the device to function properly
EN
PIN
ENLCK
7
(EXNMI)
External NMI Trap Control and Status Register
Reserved
The EXNMI trap enable bit is one of two bits
that can be used to enable NMI interrupts.
The bit is cleared by hardware at reset and
whenever the NMI interrupt occurs (EXN-
MI.EXT set). It is intended for applications
where the NMI input toggles frequently but
nested NMI traps are not desired. For these
applications, the EN bit needs to be re-en-
abled before exiting the trap handler. When
used this way, the ENLCK bit should never be
set. The EN bit can be set and cleared by soft-
ware (software can set this bit only if EXN-
MI.EXT is cleared), and should only be set
after the interrupt base register and the inter-
rupt stack pointer have been set up.
0
1
The PIN bit indicates the state (non-inverted)
on the NMI input pin. This bit is read-only, data
written into it is ignored.
0
1
The EXNMI trap enable lock bit is used to per-
manently enable NMI interrupts. Only a de-
vice reset can clear the ENLCK bit. This
allows the external NMI feature to be enabled
after the interrupt base register and the inter-
rupt stack pointer have been set up. When the
ENLCK bit is set, the EN bit is ignored.
0
1
–
–
–
–
–
–
NMI interrupts not enabled by this bit (but
may be enabled by the ENLCK bit).
NMI interrupts enabled.
NMI pin not asserted.
NMI pin asserted.
NMI interrupts not enabled by this bit (but
may be enabled by the EN bit).
NMI interrupts enabled.
3
ENLCK
2
PIN
1
EN
0
49
10.3.3
The IVCT register is a byte-wide read-only register which re-
ports the encoded value of the highest priority maskable in-
terrupt that is both asserted and enabled. The valid range is
from 10h to 2Fh. The register is read by the CPU during an
interrupt acknowledge bus cycle, and INTVECT is valid dur-
ing that time. It may contain invalid data while INTVECT is
updated.
INTVECT
10.3.4
The IENAM0 register is a word-wide read/write register
which holds bits that individually enable and disable the
maskable interrupt sources IRQ1 through IRQ15. The reg-
ister is initialized to FFFFh upon reset.
IENA
10.3.5
The IENAM1 register is a word-wide read/write register
which holds bits that individually enable and disable the
maskable interrupt sources IRQ16 through IRQ31. The reg-
ister is initialized to FFFFh at reset.
IENA
15
15
7
0
Interrupt Vector Register (IVCT)
Interrupt Enable and Mask Register 0 (IENAM0)
Interrupt Enable and Mask Register 1 (IENAM1)
6
0
The Interrupt Vector field indicates the highest
priority interrupt which is both asserted and
enabled.
Each Interrupt Enable bit enables or disables
the corresponding interrupt request IRQ1
through IRQ15, for example IENA15 controls
IRQ15. Because IRQ0 is not used, IENA0 is
ignored.
0
1
Each Interrupt Enable bit enables or disables
the corresponding interrupt request IRQ16
through IRQ31, for example IENA15 controls
IRQ31.
0
1
–
–
–
–
5
Interrupt is disabled.
Interrupt is enabled.
Interrupt is disabled.
Interrupt is enabled.
IENA
IENA
INTVECT
www.national.com
1
Res.
0
0
0