cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 31

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

7.0
The system configuration registers control and provide sta-
tus for certain aspects of device setup and operation, such
as indicating the states sampled from the ENV[2:0] inputs.
The system configuration registers are listed in Table 11.
7.1
The MCFG register is a byte-wide, read/write register that
selects the clock output features of the device.
The register must be written in active mode only, not in pow-
er save, HALT, or IDLE mode. However, the register con-
tents are preserved during all power modes.
The MCFG register format is shown below.
EXIOE
PLLCLKOE
MCLKOE
SCLKOE
Res.
7
MSTAT
MCFG
Name
MEM_IO
_SPEED
Table 11 System Configuration Registers
6
System Configuration Registers
MODULE CONFIGURATION REGISTER
(MCFG)
The EXIOE bit controls whether the external
bus is enabled in the IRE environment for im-
plementing the I/O Zone (FF FB00h
FBFFh).
0
1
The PLLCLKOE bit controls whether the PLL
clock is driven on the ENV0/PLLCLK pin.
0
1
The MCLKOE bit controls whether the Main
Clock is driven on the ENV1/CPUCLK pin.
0
1
The SCLKOE bit controls whether the Slow
Clock is driven on the ENV2/SLOWCLK pin.
0
1
MISC_IO
_SPEED
–
–
–
–
–
–
–
–
External bus disabled.
External bus enabled.
ENV0/PLLCLK pin is high impedance.
PLL clock driven on the ENV0/PLLCLK
pin.
ENV1/CPUCLK pin is high impedance.
Main Clock is driven on the ENV1/CPU-
CLK pin.
ENV2/SLOWCLK pin is high impedance.
Slow Clock is driven on the ENV2/SLOW-
CLK pin.
5
FF F914h
FF F910h
Address
Reserved
4
SCLK
OE
3
Module Configuration
Module Status
MCLK
Description
OE
2
Register
Register
PLLCLK
OE
1
–
EXI
OE
0
FF
31
MISC_IO_SPEED The MISC_IO_SPEED bit controls the slew
MEM_IO_SPEED The MEM_IO_SPEED bit controls the slew
7.2
The MSTAT register is a byte-wide, read-only register that
indicates the general status of the device. The MSTAT reg-
ister format is shown below.
OENV[2:0]
PGMBUSY The Flash Programming Busy bit is automati-
DPGMBUSY The Data Flash Programming Busy indicates
Reserved DPGMBUSY PGMBUSY OENV2 OENV1 OENV0
7
5
MODULE STATUS REGISTER (MSTAT)
rate of the output drivers for the ENV[2:0],
RDY, RFDATA, and TDO pins. To minimize
noise, the slow slew rate is recommended.
0
1
rate of the output drivers for the A[22:0], RD,
SEL[2:1], and WR[1:0] pins. Memory speeds
for the CP3BT13 are characterized with fast
slew rate. Slow slew rate reduces the avail-
able memory access time by 5 ns.
0
1
The Operating Environment bits hold the
states sampled from the ENV[2:0] input pins
at reset. These states are controlled by exter-
nal hardware at reset and are held constant in
the register until the next reset.
cally set when either the program memory or
the data memory is being programmed or
erased. It is clear when neither of the memo-
ries is busy. When this bit is set, software must
not attempt to program or erase either of
these two memories. This bit is a copy of the
FMBUSY bit in the FMSTAT register.
0
1
that the flash data memory is being erased or
a pipelined programming sequence is current-
ly ongoing. Software must not attempt to per-
form any write access to the flash program
memory at this time, without also polling the
FSMSTAT.FMFULL bit in the flash memory in-
terface. The DPGMBUSY bit is a copy of the
FMBUSY bit in the FSMSTAT register.
0
1
–
–
–
–
–
–
–
–
4
Fast slew rate.
Slow slew rate.
Fast slew rate.
Slow slew rate.
Flash memory is not busy.
Flash memory is busy.
Flash data memory is not busy.
Flash data memory is busy.
3
2
www.national.com
1
0