cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 28

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

www.national.com
6.4.2
The IOCFG register is a word-wide, read/write register that
controls the timing and bus characteristics of accesses to
the 256-byte I/O Zone memory space (FF FB00h to FF
FBFFh). The registers associated with Port B and Port C re-
side in the I/O memory array. At reset, the register is initial-
ized to 069Fh. The register format is shown below.
WAIT
HOLD
BW
IPST
BW
15
7
I/O Zone Configuration Register (IOCFG)
Reserved
6
The Memory Wait Cycles field specifies the
number of TIW (internal wait state) clock cy-
cles added for each memory access, ranging
from 000 binary for no additional TIW wait cy-
cles to 111 binary for seven additional TIW
wait cycles.
The Memory Hold Cycles field specifies the
number of T hold clock cycles used for each
memory access, ranging from 00b for no
T hold cycles to 11b for three T hold clock cy-
cles.
The Bus Width bit defines the bus width of the
IO Zone.
0
1
The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone. No idle
cycles are required for on-chip accesses.
0
1
–
–
–
–
Reserved
5
8-bit bus width.
16-bit bus width (default)
No idle cycle (recommended).
Idle cycle.
4
HOLD
3
10
2
WAIT
IPST
9
Res.
0
8
28
6.4.3
The SZCFG0 register is a word-wide, read/write register
that controls the timing and bus characteristics of Zone 0
memory accesses. Zone 0 is used for the on-chip flash
memory (including the boot area, program memory, and
data memory).
At reset, the register is initialized to 069Fh. The register for-
mat is shown below.
WAIT
HOLD
RBE
WBR
BW
FRE
IPST
BW
15
7
WBR
Static Zone 0 Configuration Register (SZCFG0)
Reserved
6
The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG0.FRE bit is set.
The Memory Hold field specifies the number
of T hold clock cycles used for each memory
access, ranging from 00b for no T hold cycles
to 11b for three T hold clock cycles. These bits
are ignored if the SZCFG0.FRE bit is set.
The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. Because the flash pro-
gram memory is required to be 16-bit bus
width, the RBE bit is a don’t care bit. This bit
is ignored when the SZCFG0.FRE bit is set.
0
1
The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG0.FRE bit is set or
when SZCFG0.RBE is clear.
0
1
The Bus Width bit controls the bus width of the
zone. The flash program memory must be
configured for 16-bit bus width.
0
1
The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read op-
eration takes one clock cycle. A normal read
operation takes at least two clock cycles.
0
1
The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone. No idle
cycles are required for on-chip accesses.
0
1
–
–
–
–
–
–
–
–
–
–
RBE
Burst read disabled.
Burst read enabled.
No TBW on burst read cycles.
One TBW on burst read cycles.
8-bit bus width.
16-bit bus width (required).
Normal read cycles.
Fast read cycles.
No idle cycle (recommended).
Idle cycle inserted.
5
12
4
HOLD
FRE
11
3
IPRE IPST
10
2
WAIT
9
Res.
0
8