cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 43

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

ed. The maximum bus throughput in intermittent mode is
one transfer for every three System Clock cycles. The max-
imum bus throughput in continuous mode is one transfer for
every clock cycle.
The I/O device which made the DMA request is called the
implied I/O device. The other device can be either memory
or another I/O device, and is called the addressed device.
Because only one address is required in direct mode, this
address is taken from the corresponding ADCAn counter.
The DMAC channel generates either a read or a write bus
cycle, as controlled by the DMACNTLn.DIR bit.
When the DMACNTLn.DIR bit is clear, a read bus cycle
from the addressed device is performed, and the data is
written to the implied I/O device. When the DMACNTLn.DIR
bit is set, a write bus cycle to the addressed device is per-
formed, and the data is read from the implied I/O device.
The configuration of either address freeze or address up-
date (increment or decrement) is independent of the num-
ber of transferred bytes, transfer direction, or number of
bytes in each DMAC transfer cycle. All these can be config-
ured for each channel by programming the appropriate con-
trol register.
Whether 8 or 16 bits are transferred in each cycle is select-
ed by the DMACNTLn.TCS register bit. After the data item
has been transferred, the BLTCn counter is decremented by
one. The ADCAn counter is updated according to the INCA
and ADA fields in the DMACNTLn register.
9.2.2
In indirect (memory-to-memory) mode, data transfers use
two consecutive bus cycles. The data is first read into a tem-
porary register, and then written to the destination in the fol-
lowing cycle. This mode is slower than the direct (flyby)
mode, but it provides support for different source and desti-
nation bus widths. Indirect mode must be used for transfers
between memory devices.
If an intermittent bus policy is used, the maximum through-
put is one transfer for every five clock cycles. If a continuous
bus policy is used, maximum throughput is one transfer for
every two clock cycles.
When the DMACNTLn.DIR bit is 0, the first bus cycle reads
data from the source using the ADCAn counter, while the
second bus cycle writes the data into the destination using
the ADCBn counter. When the DMACNTLn.DIR bit is set,
the first bus cycle reads data from the source using the AD-
CBn counter, while the second bus cycle writes the data into
the destination addressed by the ADCAn counter.
The number of bytes transferred in each cycle is taken from
the DMACNTLn.TCS register bit. After the data item has
been transferred, the BLTCn counter is decremented by
one. The ADCAn and ADCBn counters are updated accord-
ing to the INCA, INCB, ADA, and ADB fields in the
DMACNTLn register.
Indirect (Memory-To-Memory) Transfers
43
9.3
The DMAC operates in three different block transfer modes:
single transfer, double buffer, and auto-initialize.
9.3.1
This mode provides the simplest way to accomplish a single
block data transfer.
Initialization
Termination
When the BLTCn counter reaches 0:
The DMACNTLn.CHEN bit must be cleared before loading
the DMACNTLn register to avoid prematurely starting a new
DMA transfer.
9.3.2
This mode allows software to set up the next block transfer
while the current block transfer proceeds.
Initialization
Continuation/Termination
When the BLTCn counter reaches 0:
If the DMASTAT.VLD bit is set:
1. Write the block transfer addresses and byte count into
2. Clear the DMACNTLn.OT bit to select non-auto-initial-
3. Set the DMACNTLn.CHEN bit to activate the channel
1. The transfer operation terminates.
2. The DMASTAT.TC and DMASTAT.OVR bits are set, and
3. An
1. Write the block transfer addresses and byte count into
2. Clear the DMACNTLn.OT bit to select non-auto-initial-
3. Set the DMACNTLn.CHEN bit. This activates the chan-
4. While the current block transfer proceeds, write the ad-
1. The DMASTAT.TC bit is set.
2. An
3. The DMAC channel checks the value of the VLD bit.
1. The channel copies the ADRAn, ADRBn, and BLTRn
2. The DMASTAT.VLD bit is cleared.
3. The next block transfer is started.
the corresponding ADCAn, ADCBn, and BLTCn
counters.
ize mode. Clear the DMASTAT.VLD bit by writing a 1 to
it.
and enable it to respond to DMA transfer requests.
the DMASTAT.CHAC bit is cleared.
DMACNTLn.ETC or DMACNTLn.EOVR bits.
the ADCAn, ADCBn, and BLTCn counters.
ize mode. Clear the DMASTAT.VLD bit by writing a 1 to
it.
nel and enables it to respond to DMA transfer requests.
dresses and byte count for the next block into the
ADRAn, ADRBn, and BLTRn registers. The BLTRn reg-
ister must be written last, because it sets the DMAS-
TAT.VLD bit which indicates that all the parameters for
the next transfer have been updated.
DMACNTLn.ETC bit.
values into the ADCAn, ADCBn, and BLTCn registers.
OPERATION MODES
Single Transfer Operation
Double Buffer Operation
interrupt
interrupt
is
is
generated
generated
if
if
enabled
enabled
www.national.com
by
by
the
the