cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 54

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

www.national.com
The Stop Main Osc signal from the Power Management
Module stops and starts the high-frequency oscillator.
When this signal is asserted, it presets the 14-bit timer to
3FFFh and stops the high-frequency oscillator. When the
signal goes inactive, the high-frequency oscillator starts and
the 14-bit timer counts down from its preset value. When the
timer reaches zero, it stops counting and asserts the Good
Main Clock signal.
11.3
The Slow Clock is necessary for operating the device in re-
duced power modes and to provide a clock source for mod-
ules such as the Timing and Watchdog Module.
The Slow Clock operates in a manner similar to the Main
Clock. The Stop Slow Osc signal from the Power Manage-
ment Module stops and starts the low-frequency (32.768
kHz) oscillator. When this signal is asserted, it presets a 6-
bit timer to 3Fh and disables the low-frequency oscillator.
When the signal goes inactive, the low-frequency oscillator
starts, and the 6-bit timer counts down from its preset value.
When the timer reaches zero, it stops counting and asserts
the Good Slow Clock signal, which indicates that the Slow
Clock is stable.
For systems that do not require a reduced power consump-
tion mode, the external crystal network may be omitted for
the Slow Clock. In that case, the Slow Clock can be synthe-
sized by dividing the Main Clock by a prescaler factor. The
prescaler circuit consists of a fixed divide-by-2 counter and
a programmable 8-bit prescaler register. This allows a
choice of clock divisors ranging from 2 to 512. The resulting
Slow Clock frequency must not exceed 100 kHz.
A software-programmable multiplexer selects either the
prescaled Main Clock or the 32.768 kHz oscillator as the
Slow Clock. At reset, the prescaled Main Clock is selected,
ensuring that the Slow Clock is always present initially. Se-
lection of the 32.768 kHz oscillator as the Slow Clock dis-
ables the clock prescaler, which allows the CLK1 oscillator
to be turned off, which reduces power consumption and ra-
diated emissions. This can be done only if the module de-
tects a toggling low-speed oscillator. If the low-speed
oscillator is not operating, the prescaler remains available
as the Slow Clock source.
11.4
The PLL Clock is generated by the PLL from the 12 MHz
Main Clock by applying a multiplication factor of ×3, ×4, or
×5.
To enable the PLL:
1. Set the PLL multiplication factor in PRFSC.MODE.
2. Clear the PLL power-down bit CRCTRL.PLLPWD.
3. Clear the high-frequency clock select bit CRC-
TRL.FCLK.
4. Read CRCTRL.FCLK, and go back to step 3 if not clear.
The CRCTRL.FCLK bit will be clear only after the PLL has
stabilized, so software must repeat step 3 until the bit is
clear. The clock source can be switched back to the Main
Clock by setting the CRCTRL.FCLK bit.
SLOW CLOCK
PLL CLOCK
54
The PRSFC register must not be modified while the System
Clock is derived from the PLL Clock. The System Clock
must be derived from the low-frequency oscillator clock
while the MODE field is modified.
11.5
The System Clock drives most of the on-chip modules, in-
cluding the CPU. Typically, it is driven by the Main Clock, but
it can also be driven by the PLL. In either case, the clock sig-
nal is passed through a programmable divider (scale factors
from ÷1 to ÷16).
11.6
Auxiliary Clock 1 and Auxiliary Clock 2 are generated from
Main Clock for use by certain peripherals. Auxiliary Clock 1
is available for the Bluetooth controller and the Advanced
Audio Interface. Auxiliary Clock 2 is available for the CVSD/
PCM transcoder. The Auxiliary clocks may be configured to
keep these peripherals running when the System Clock is
slowed down or suspended during low-power modes.
11.7
The Power-On Reset circuit generates a system reset signal
at power-up and holds the signal active for a period of time
to allow the crystal oscillator to stabilize. The circuit detects
a power turn-on condition, which presets a 14-bit timer driv-
en by Main Clock to a value of 3FFFh. This preset value is
defined in hardware and not programmable. Once oscilla-
tion starts and the clock becomes active, the timer starts
counting down. When the count reaches zero, the 14-bit
timer stops counting and the internal reset signal is deacti-
vated (unless the RESET pin is held low).
The circuit sets a power-on reset bit upon detection of a
power-on condition. The CPU can read this bit to determine
whether a reset was caused by a power-up or by the RESET
input.
Note: The Power-On Reset circuit cannot be used to detect
a drop in the supply voltage.
11.8
An active-low reset input pin called RESET allows the de-
vice to be reset at any time. When the signal goes low, it
generates an internal system reset signal that remains ac-
tive until the RESET signal goes high again.
If the VCC power supply has slow rise-time. it may be nec-
essary to use an external reset circuit to insure proper de-
vice initialization. Figure 5 shows an example of an external
reset circuit.
SYSTEM CLOCK
AUXILIARY CLOCKS
POWER-ON RESET
EXTERNAL RESET
IOVCC
Figure 5. External Reset Circuit
R
C
IOVCC
RESET
GND
CP3BT1x
DS151