cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 144

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

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20.3
In Slave mode, the MSK pin is an input for the shift clock
MSK. MDIDO is placed in TRI-STATE mode when MWCS is
inactive. Data transfer is enabled when MWCS is active.
The slave starts driving MDIDO when MWCS is activated.
The most significant bit (lower byte in 8-bit mode or upper
byte in 16-bit mode) is output onto the MDIDO pin first. After
eight or sixteen clocks (depending on the selected mode),
the data transfer is completed.
If a new shift process starts before MWDAT was written, i.e.,
while MWDAT does not contain any valid data, and the
“Echo Enable” (ECHO) bit is set, the data received from
MDODI is transmitted on MDIDO in addition to being shifted
to MWDAT. If the ECHO bit is clear, the data transmitted on
MDIDO is the data held in the MWDAT register, regardless
of its validity. The master may negate the MWCS signal to
synchronize the bit count between the master and the slave.
In the case that the slave is the only slave in the system,
MWCS can be tied to VSS.
20.4
An interrupt is generated in any of the following cases:
T When the read buffer is full (RBF = 1) and the “Enable In-
T Whenever the shifter is not busy, i.e. the BSY bit is clear
T When an overrun condition occurs (OVR is set) and the
In addition, MWCS is an input to the MIWU (see
Section 13.0), which can be programmed to generate an
edge-triggered interrupt.
terrupt for Read” bit is set (EIR = 1).
(BSY = 0) and the “Enable Interrupt for Write” bit is set
(EIW = 1).
“Enable Interrupt on Overrun” bit is set (MEIO = 1). This
usage is restricted to master mode.
SLAVE MODE
INTERRUPT GENERATION
Data Out
Data In
MSK
MSB
MSB
Sample
Point
Shift
Out
MSB - 1
MSB - 1
Figure 76. Alternate Mode (SCIDL = 1)
MSB - 2
MSB - 2
144
Figure 77 illustrates the various interrupt capabilities of this
module.
20.5
Software interacts with the Microwire interface by accessing
the Microwire registers. There are three such registers:
20.5.1
The MWDAT register is a word-wide, read/write register
used to transmit and receive data through the MDODI and
MDIDO pins. Figure 78 shows the hardware structure of the
register.
MWCTL1
MWSTAT
MWDAT
Name
Table 63 Microwire Interface Registers
MICROWIRE INTERFACE REGISTERS
Microwire Data Register (MWDAT)
OVR = 1
RBF = 1
BSY = 0
Figure 77. MWSPI Interrupts
Bit 1
Bit 1
FF FE60h
FF FE62h
FF FE64h
Address
EIW
EIO
EIR
(LSB)
(LSB)
Bit 0
Bit 0
End of Transfer
DS072
Microwire Control
Microwire Status
Microwire Data
Description
Register
Register
Register
MWSPI
Interrupt
DS073