cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 55

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

The value of R should be less than 50K ohms. The RC time
constant of the circuit should be 5 times the power supply
rise time. The time constant also should exceed the stabili-
zation time for the high-frequency oscillator.
11.9
Table 25 lists the clock and reset registers.
11.9.1
The CRCTRL register is a byte-wide read/write register that
controls the clock selection and contains the power-on reset
status bit. At reset, the CRCTRL register is initialized as de-
scribed below:
SCLK
FCLK
Reserved
7
CRCTRL
PRSFC
PRSSC
PRSAC
Name
6
CLOCK AND RESET REGISTERS
Clock and Reset Control Register (CRCTRL)
Table 25 Clock and Reset Registers
POR ACE2 ACE1 PLLPWD FCLK SCLK
The Slow Clock Select bit controls the clock
source used for the Slow Clock.
0
1
The Fast Clock Select bit selects between the
12 MHz Main Clock and the PLL as the source
used for the System Clock. After reset, the
Main Clock is selected. Attempting to switch to
the PLL while the PLLPWD bit is set (PLL is
turned off) is ignored. Attempting to switch to
the PLL also has no effect if the PLL output
clock has not stabilized.
0
1
5
–
–
–
–
Slow Clock driven by prescaled Main
Clock.
Slow Clock driven by 32.768 kHz oscilla-
tor.
The System Clock prescaler is driven by
the output of the PLL.
The System Clock prescaler is driven by
the 12-MHz Main Clock. This is the de-
fault after reset.
FF FC40h
FF FC42h
FF FC44h
FF FC46h
Address
4
3
High Frequency Clock
Low Frequency Clock
Prescaler Register
Prescaler Register
Prescaler Register
2
Clock and Reset
Control Register
Auxiliary Clock
Description
1
0
55
PLLPWD
ACE1
ACE2
POR
The PLL Power-Down bit controls whether the
PLL is active or powered down (Stop PLL sig-
nal asserted). When this bit is set, the on-chip
PLL stays powered-down. Otherwise it is pow-
ered-up or it can be controlled by the Power
Management Module, respectively. Before
software can power-down the PLL in Active
mode by setting the PLLPWD bit, the FCLK bit
must be set. Attempting to set the PLLPWD
bit while the FCLK bit is clear is ignored. The
FCLK bit cannot be cleared until the PLL clock
has stabilized. After reset this bit is set.
0
1
When the Auxiliary Clock Enable bit is set and
a stable Main Clock is provided, the Auxiliary
Clock 1 prescaler is enabled and generates
the first Auxiliary Clock. When the ACE1 bit is
clear or the Main Clock is not stable, Auxiliary
Clock 1 is stopped. Auxiliary Clock 1 is used
as the clock input for the Bluetooth LLC and
the audio interface. After reset this bit is clear.
0
1
When the Auxiliary Clock Enable 2 bit is set
and a stable Main Clock is provided, the Aux-
iliary Clock 2 prescaler is enabled and gener-
ates Auxiliary Clock 2. When the ACE2 bit is
clear or the Main Clock is not stable, the Aux-
iliary Clock 2 is stopped. Auxiliary Clock 2 is
used as the clock input for the CVSD/PCM
transcoder. After reset this bit is clear.
0
1
Power-On-Reset - The Power-On-Reset bit is
set when a power-turn-on condition has been
detected. This bit can only be cleared by soft-
ware, not set. Writing a 1 to this bit will be ig-
nored, and the previous value of the bit will be
unchanged.
0
1
–
–
–
–
–
–
–
–
PLL is active.
PLL is powered down.
Auxiliary Clock 1 is stopped.
Auxiliary Clock 1 is active if the Main
Clock is stable.
Auxiliary Clock 2 is stopped.
Auxiliary Clock 2 is active if the Main
Clock is stable.
Software cleared this bit.
Software has not cleared his bit since the
last reset.
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