cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 39

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

DERR
8.5.8
The FMPSR register is a byte-wide read/write register that
selects the prescaler divider ratio. The CPU must not modify
this register while an erase or programming operation is in
progress (FMBUSY is set). At reset, this register is initial-
ized to 04h if the flash memory is idle. The CPU bus master
has read/write access to this register.
FTDIV
8.5.9
The FMSTART/FSMSTART register is a byte-wide read/
write register that controls the program/erase start delay
time. Software must not modify this register while a pro-
gram/erase operation is in progress (FMBUSY set). At re-
set, this register is initialized to 18h if the flash memory is
idle. The CPU bus master has read/write access to this reg-
ister.
FTSTART
7
7
Reserved
Flash Memory Prescaler Register (FMPSR/
FSMPSR)
(FMSTART/FSMSTART)
Flash Memory Start Time Reload Register
The Data Loss Error bit indicates that a buffer
overrun has occurred during a programming
sequence. After a data loss error occurs, soft-
ware can clear the DERR bit by writing a 1 to
it. Writing a 0 to the DERR bit has no effect.
Software must not change this bit while the
flash program memory is busy being pro-
grammed or erased.
0
1
The prescaler divisor scales the frequency of
the System Clock by a factor of (FTDIV + 1).
The Flash Timing Start Delay Count field gen-
erates a delay of (FTSTART + 1) prescaler
output clocks.
–
–
No data loss error occurred.
Data loss error occurred.
5
FTSTART
4
FTDIV
0
0
39
8.5.10
The FMTRAN/FMSTRAN register is a byte-wide read/write
register that controls some program/erase transition times.
Software must not modify this register while program/erase
operation is in progress (FMBUSY set). At reset, this regis-
ter is initialized to 30h if the flash memory is idle. The CPU
bus master has read/write access to this register.
FTTRAN
8.5.11
The FMPROG/FSMPROG register is a byte-wide read/write
register that controls the programming pulse width. Soft-
ware must not modify this register while a program/erase
operation is in progress (FMBUSY set). At reset, this regis-
ter is initialized to 16h if the flash memory is idle. The CPU
bus master has read/write access to this register.
FTPROG
8.5.12
The FMPERASE/FSMPERASE register is a byte-wide
read/write register that controls the page erase pulse width.
Software must not modify this register while a program/
erase operation is in progress (FMBUSY set). At reset, this
register is initialized to 04h if the flash memory is idle. The
CPU bus master has read/write access to this register.
FTPER
7
7
7
Flash Memory Transition Time Reload
Register (FMTRAN/FSMTRAN)
Flash Memory Programming Time Reload
Register (FMPROG/FSMPROG)
Flash Memory Page Erase Time Reload
Register (FMPERASE/FSMPERASE)
The Flash TIming Transition Count field spec-
ifies a delay of (FTTRAN + 1) prescaler output
clocks.
The Flash Timing Programming Pulse Width
field specifies a programming pulse width of
8 × (FTPROG + 1) prescaler output clocks.
The Flash Timing Page Erase Pulse Width
field specifies a page erase pulse width of
4096 u(FTPER + 1) prescaler output clocks.
FTPROG
FTTRAN
FTPER
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0
0
0